Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 8184475 | Robust local bit select circuitry to overcome timing mismatch An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which... | 05/22/2012 |
| 8183950 | Auto-calibration for ring oscillator VCO A phase locked loop (“PLL”) includes a voltage controlled oscillator (“VCO”) operable to acquire and maintain lock at a selected output frequency of the VCO and control logic operable to perform steps in a method of selecting a frequency band for operating t... | 05/22/2012 |
| 8183949 | Compensation of VCO gain curve offsets using auto-calibration A method is provided for selecting an operating band of a voltage-controlled oscillator (“VCO”) of a phase locked loop (“PLL”) for which the lock frequency is closest to a center of the frequency range of the operating band. In such method, steps can be perf... | 05/22/2012 |
| 8144726 | Structure for out of band signaling enhancement for high speed serial driver A design structure is provided for a microelectronic serial driver. The serial driver is operable to transmit a differential pattern signal during a burst interval and a predetermined common mode voltage level during a second interval between adjacent burst interval... | 03/27/2012 |
| 8127157 | System and method of controlling an operating frequency in an electronic system A method and apparatus for adaptively adjusting the operating voltage of an integrated circuit in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations, or reliability wearout mechanisms. The minimum opera... | 02/28/2012 |
| 8053823 | Simplified buried plate structure and process for semiconductor-on-insulator chip A structure is provided herein which includes an array of trench capacitors having at least portions disposed below a buried oxide layer of an SOI substrate. Each trench capacitor shares a common unitary buried capacitor plate which includes at least a portion of a ... | 11/08/2011 |
| 8021945 | Bottle-shaped trench capacitor with enhanced capacitance In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric lay... | 09/20/2011 |
| 8018818 | Systems and methods for storing and reading data in a data storage system Systems and methods for storing and reading data in a data storage system are provided. The data storage system includes a storage medium for storing data. The storage medium stores data as a plurality of topographical features. Further, the data storage system incl... | 09/13/2011 |
| 8009268 | Immersion optical lithography system having protective optical coating An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an artic... | 08/30/2011 |
| 7961605 | System and method for enabling management of a plurality of messages in a communication network A method and system for enabling management of a plurality of messages in a communication network is provided. The method includes measuring an in-load and an out-service corresponding to a plurality of switching-nodes in the communication network. The method furthe... | 06/14/2011 |
| 7955921 | Full silicide gate for CMOS A method is provided for fabricating an n-type field effect transistor (“NFET”) and a p-type field effect transistor (“PFET”) in which the NFET and PFET are formed after which a protective hard mask layer, e.g., a dielectric stressor layer is formed to overl... | 06/07/2011 |
| 7943454 | Method for dual stress liner A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included... | 05/17/2011 |
| 7928513 | Protection against charging damage in hybrid orientation transistors A chip can include a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. An ... | 04/19/2011 |
| 7923836 | BLM structure for application to copper pad A microelectronic element and a related method for fabricating such is provided. The microelectronic element comprises a contact pad overlying a major surface of a substrate. The contact pad has a composition including copper at a contact surface. A passivation laye... | 04/12/2011 |
| 7888197 | Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate. In such method an SOI substrate is formed to include (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (iii) a buried oxide (“BOX... | 02/15/2011 |
| 7879650 | Method of providing protection against charging damage in hybrid orientation transistors In a method of fabricating a CMOS structure, a bulk device can be formed in a first region in conductive communication with an underlying bulk region of the substrate. A first gate conductor may overlie the first region. An SOI device can be formed which has a sourc... | 02/01/2011 |
| 7840916 | Structure for on-chip electromigration monitoring system A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for examp... | 11/23/2010 |
| 7833872 | Uniform recess of a material in a trench independent of incoming topography Columnar elements which extend to varying heights above a major surface of a substrate, e.g., polysilicon studs within trenches in the substrate, are recessed to a uniform depth below the major surface. The columnar elements are etched selectively with respect to a ... | 11/16/2010 |
| 7818692 | Automated optimization of device structure during circuit design stage A method of improving a circuit design for a very large scale integrated circuit is provided which represents a plurality of semiconductor devices interconnected in a circuit. It is determined whether an edge of a feature of one of the plurality of semiconductor dev... | 10/19/2010 |
| 7785944 | Method of making double-gated self-aligned finFET having gates of different lengths A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least sub... | 08/31/2010 |
| 7772096 | Formation of SOI by oxidation of silicon with engineered porosity gradient A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type ... | 08/10/2010 |
| 7768041 | Multiple conduction state devices having differently stressed liners A field effect transistor (“FET”) is provided which includes an active semiconductor region including a channel region, a first source-drain region and a second source-drain region. A major surface of the active semiconductor region is divided into a mutually ex... | 08/03/2010 |
| 7767537 | Simplified method of fabricating isolated and merged trench capacitors Trench capacitors having small and large sizes can be formed simultaneously using a combined lithography process in which openings in a photomask have the same dimensions and spacings. Larger capacitors are formed when the openings in the photomask are aligned with ... | 08/03/2010 |
| 7759739 | Transistor with dielectric stressor elements A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a dire... | 07/20/2010 |
| 7759188 | Method of fabricating vertical body-contacted SOI transistor A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a... | 07/20/2010 |
| 7733964 | Automatic adaptive equalization method for high-speed serial transmission link In a method for performing equalization of a communication system, a predetermined signal can be transmitted from a transmitter unit to a receiver unit in a downchannel direction on a transmission line, for example as a pair of differential signals which simultaneou... | 06/08/2010 |
| 7719302 | On-chip electromigration monitoring A method is provided for monitoring interconnect resistance within a semiconductor chip assembly, A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals i... | 05/18/2010 |
| 7692439 | Structure for modeling stress-induced degradation of conductive interconnects A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfac... | 04/06/2010 |
| 7686886 | Controlled shape semiconductor layer by selective epitaxy under seed structure A method for forming a structure of a desired cross-section on a substrate is provided. The method provides a seed structure comprising at least one support layer on the substrate. The support layer has a geometric shape related to the desired cross-section of the s... | 03/30/2010 |
| 7662722 | Air gap under on-chip passive device A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic ... | 02/16/2010 |
| 7661039 | Self-synchronizing bit error analyzer and circuit A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler t... | 02/09/2010 |
| 7660350 | High-speed multi-mode receiver A data receiver is provided which is operable to receive a signal controllably pre-distorted and transmitted by a transmitter, to generate information for adjusting the pre-distortion applied to the signal transmitted by the transmitter, and to transmit the informat... | 02/09/2010 |
| 7659581 | Transistor with dielectric stressor element fully underlying the active semiconductor region A compressive stress is applied to a channel region of a PFET by structure including a discrete dielectric stressor element that fully underlies the bottom surface of an active semiconductor region in which the source, drain and channel region of the PFET is dispose... | 02/09/2010 |
| 7646469 | Immersion optical lithography system having protective optical coating An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an artic... | 01/12/2010 |
| 7639032 | Structure for monitoring stress-induced degradation of conductive interconnects A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metal... | 12/29/2009 |
| 7632724 | Stressed SOI FET having tensile and compressive device regions A method is provided for fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of ... | 12/15/2009 |
| 7629202 | Method and apparatus for electrostatic discharge protection using a temporary conductive coating A method and apparatus for providing ESD protection of an integrated circuit using a temporary conductive coating. The method deposits a temporary conductive coating upon a chip die between contacts to be protected such that a conductive path is created between cont... | 12/08/2009 |
| 7615457 | Method of fabricating self-aligned bipolar transistor having tapered collector A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, th... | 11/10/2009 |
| 7612414 | Overlapped stressed liners for improved contacts A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a... | 11/03/2009 |
| 7586806 | SRAM active write assist method for improved operational margins A method is provided for controlling a voltage level supplied to a static random access memory (“SRAM”). In such method, when a column of the SRAM is selected for writing, a first p-type field effect transistor (“PFET”) and a second PFET can be operated to s... | 09/08/2009 |
