Famous Patents
3M employee and church chorister Art Fry needed something to temporarily mark pages in his hymnal. He was in luck because his colleague, Spencer Silver, accidentally developed a glue that was too weak for other purposes. After initially discouraging consumer response, Post-it Notes became a hit in 1979.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8040813 | Apparatus and method for reduced loading of signal transmission elements An apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. The signal-handling elemen... | 10/18/2011 |
| 8024679 | Structure for apparatus for reduced loading of signal transmission elements A design structure for a signal-handing apparatus or communication apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling eleme... | 09/20/2011 |
| 7989298 | Transistor having V-shaped embedded stressor A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gat... | 08/02/2011 |
| 7920282 | Job preempt set generation for resource management A method is provided for prioritizing jobs in a computing environment having a plurality of nodes sharing one or more resources. Such method includes, given a job A to be scheduled having certain resource requirements, generating a list P of already scheduled jobs w... | 04/05/2011 |
| 7914949 | Method for testing a photomask A method, a recording medium and an apparatus for testing a photomask are provided. In the disclosed method, a particular region of a photomask is selected, either from a physical instance of the photomask, or from the photomask as represented by a digital represent... | 03/29/2011 |
| 7847402 | BEOL interconnect structures with improved resistance to stress A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation... | 12/07/2010 |
| 7802102 | Method for efficient and secure data migration between data processing systems The present invention provides a method for transferring encrypted information from one storage area to other storage area wherein cryptographic data protection scheme having protection attributes are applied on the data. A crypto container having cryptographic prop... | 09/21/2010 |
| 7787367 | Method and a system for flow control in a communication network The present invention relates to a method and a system of flow control in a communication network. The method comprises determining if at least one sender buffer has a sufficient number of credits. The sufficient number of credits informs the sender buffer if the re... | 08/31/2010 |
| 7777296 | Nano-fuse structural arrangements having blow protection barrier spaced from and surrounding fuse link A nano-fuse structural arrangement, includes, for example, a semiconductor substrate having an electrically conductive region formed thereon; an electrically conductive elongated nano-structure having a maximum diameter of less than approximately 50 nm and a maximum... | 08/17/2010 |
| 7776695 | Semiconductor device structure having low and high performance devices of same conductive type on same substrate A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first ga... | 08/17/2010 |
| 7741166 | Oxidation method for altering a film structure A method is provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed o... | 06/22/2010 |
| 7734677 | Method, system and program product for dynamically integrating backend systems into a J2EE application server environment A method, system and program product is provided for dynamically integrating Backend System instances into a J2EE application server environment during runtime without having to restart the J2EE application server environment. The system comprises a deployment descr... | 06/08/2010 |
| 7718514 | Method of forming a guard ring or contact to an SOI substrate A method is provided of forming a conductive via in contact with a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region. The trench isolation region may sh... | 05/18/2010 |
| 7709930 | Tuneable semiconductor device with discontinuous portions in the sub-collector Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a ba... | 05/04/2010 |
| 7669057 | Secure computer password system and method An enhanced security method is provided for accessing information from a second computer using a password at a first computer. According to such method, a password used for accessing information is inputted to the first computer and stored on the first computer. The... | 02/23/2010 |
| 7650469 | Determining whether a non-running processor has access to an address space A method is provided for determining whether a logical processor of an information processing system has access to an address space of the information processing system. An instruction is issued by a first processor, the instruction referencing a target logical proc... | 01/19/2010 |
| 7562337 | OPC verification using auto-windowed regions A method is provided for performing optical proximity correction (“OPC”) verification in which features of concern of a photomask are identified using data relating to shapes of the photomask, an aerial image to be obtained using the photomask, or a photoresist ... | 07/14/2009 |
| 7560966 | Method of testing connectivity using dual operational mode CML latch A method of testing connectivity through a plurality of dual purpose current mode logic (“CML”) latch circuits connected in a series is provided. Each of the CML latch circuits are operable to latch at least one output signal at a timing in accordance with at le... | 07/14/2009 |
| 7553232 | System and method for predicting results of chance events over a user-selected number of events A method, a system, and a recording medium are provided herein by which a user selects a number of a plurality of events for which an outcome of each event is not known to the user. A predicted result is then automatically indicated to the user based on a probabilit... | 06/30/2009 |
| 7547608 | Polysilicon hard mask for enhanced alignment signal A method is provided for forming a polysilicon layer on a substrate and aligning an exposure system with an alignment feature of the substrate through the polysilicon layer. In such method, a polysilicon layer is deposited over the substrate having the alignment fea... | 06/16/2009 |
| 7541065 | Method of forming film stack having under layer for preventing pinhole defects A method is provided for forming a film stack in which a first film including a first polymer is formed on a substrate. A second film, which can include a second polymer other than the first polymer, is formed to have an inner surface disposed on the first film. The... | 06/02/2009 |
| 7534667 | Structure and method for fabrication of deep junction silicon-on-insulator transistors A structure and method for fabricating a transistor structure is provided. The method comprises the steps of: (a) providing a substrate including a semiconductor-on-insulator (“SOI”) layer separated from a bulk region of the substrate by a buried dielectric laye... | 05/19/2009 |
| 7528451 | CMOS gate conductor having cross-diffusion barrier A gate conductor is provided for a transistor pair including an n-type field effect transistor (“NFET”) having an NFET active semiconductor region and a p-type field effect transistor (“PFET”) having a PFET active semiconductor region, where the NFET and PFE... | 05/05/2009 |
| 7515489 | SRAM having active write assist for improved operational margins A static random access memory (SRAM) is provided which includes a plurality of columns and a plurality of cells arranged therein. A voltage control circuit can be used to temporarily reduce a voltage at which power is supplied to cells belonging to a column selected... | 04/07/2009 |
| 7495743 | Immersion optical lithography system having protective optical coating An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an artic... | 02/24/2009 |
| 7492016 | Protection against charging damage in hybrid orientation transistors A chip includes a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. A SOI ... | 02/17/2009 |
| 7491588 | Method and structure for buried circuits and devices A method is provided in which for fabricating a complementary metal oxide semiconductor (CMOS) circuit on a semiconductor-on-insulator (SOI) substrate. A plurality of field effect transistors (FETs) are formed, each having a channel region disposed in a common devic... | 02/17/2009 |
| 7485519 | After gate fabrication of field effect transistor having tensile and compressive regions A field effect transistor (“FET”) is formed to include a stress in a channel region of an active semiconductor region of an SOI substrate. A gate is formed to overlie the active semiconductor region, after which a sacrificial stressed layer is formed which overl... | 02/03/2009 |
| 7485525 | Method of manufacturing a multiple port memory having a plurality of parallel connected trench capacitors in a cell An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of c... | 02/03/2009 |
| 7482673 | Structure and method for bipolar transistor having non-uniform collector-base junction A bipolar transistor is provided which includes a collector region, an intrinsic base region overlying the collector region and an emitter region overlying the intrinsic base region. An extrinsic base overlies a portion of the intrinsic base region. An epitaxial spa... | 01/27/2009 |
| 7476938 | Transistor having dielectric stressor elements at different depths from a semiconductor surface for applying shear stress A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a dire... | 01/13/2009 |
| 7466604 | SRAM voltage control for improved operational margins A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portio... | 12/16/2008 |
| 7462547 | Method of fabricating a bipolar transistor having reduced collector-base capacitance A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the ep... | 12/09/2008 |
| 7447273 | Redundancy structure and method for high-speed serial link An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are ... | 11/04/2008 |
| 7439568 | Vertical body-contacted SOI transistor A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate i... | 10/21/2008 |
| 7430167 | Method and system to enable an adaptive load balancing in a parallel packet switch A method and a system to adapt the load balancing of the incoming traffic over the planes of a parallel packet switch (PPS) on the basis of the monitoring of requests and acknowledgments exchanged between ingress port adapters and arrays of collapsed virtual output ... | 09/30/2008 |
| 7405898 | System and method for generating a position error signal (PES) reference curve in a data storage device System and method for generating a Position Error Signal (PES) reference curve in data storage devices are provided. The method includes scanning a distance of at least one Track Pitch (TP) in a cross-track direction in each servo-burst along a predefined path. One ... | 07/29/2008 |
| 7405678 | Method of retrieving data from a storage device using a recovered read-back parameter A storage device comprising a modulation encoder and decoder, an error-correction encoder and decoder, and a metric computation module. The modulation encoder and decoder provide a modulation code for data stored on the storage device. The error-correction encoder a... | 07/29/2008 |
| 7404115 | Self-synchronising bit error analyser and circuit A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator... | 07/22/2008 |
| 7378853 | System and method for detecting cable faults for high-speed transmission link A system and method of detecting a fault in a transmission link are provided which includes providing a selectable reference level according to one of a direct current (DC) mode threshold and an alternating current (AC) mode threshold, wherein the DC mode threshold ... | 05/27/2008 |
