Quotables
"What, sir, would you make a ship sail against the wind and currents by lighting a bonfire under her deck? I pray you, excuse me, I have not the time to listen to such nonsense."
Napoleon Bonaparte ; When told of the Robert Fulton steamboat
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7685248 | User interface in data forwarding network Methods and apparatus, including computer program products, for data forwarding storage. A user system communicates with a network of interconnected computer system nodes. The user system includes an input/output device including a user interface to initiate the sen... | 03/23/2010 |
| 7305467 | Autonomous tracking wireless imaging sensor network including an articulating sensor and automatically organizing network nodes A wireless integrated network sensor (WINS) system is provided that integrates articulating tracking systems with WINS network components including visual or infrared sensors and imaging devices to enable precise tracking and targeting of objects moving through a se... | 12/04/2007 |
| 7292678 | Voice activated, voice responsive product locator system, including product location method utilizing product bar code and aisle-situated, aisle-identifying bar code The present invention is an item location system which relies upon voice activation and responsiveness to identify location(s) of item(s) sought by a user. The system includes a continuous speech recognition digital signal processor, a programmable microprocessor in... | 11/06/2007 |
| 5721438 | Heterojunction semiconductor device and method of manufacture A heterojunction bipolar transistor (HBT) (30) is formed to have a germanium composition profile (46) in a base region (32) that improves the tolerance of the HBT device (30) to manufacturing variations and reduces the sensitivity to emitter/base biases. ... | 02/24/1998 |
| 5703808 | Non-volatile memory cell and method of programming The programming time of a non-volatile memory cell (13) is reduced by forming the non-volatile memory cell (13) in a well region (12). The presence of the well region (12) increases the number of electrons that are present in a channel region (14) of the ... | 12/30/1997 |
| 5703493 | Wafer holder for semiconductor applications A semiconductor substrate (15) is placed into a recessed area (12) of a support structure (10). A ring (20) is then placed on the support structure (10) to form a wafer holder (30) which provides support to the semiconductor substrate (15) during handling... | 12/30/1997 |
| 5675166 | FET with stable threshold voltage and method of manufacturing the same A low voltage field effect transistor structure (20) is provided with a threshold voltage that is tolerant of process variations that alter the location of a source implant region (41). A first halo region (33) and a second halo region (36) are formed adj... | 10/07/1997 |
| 5659950 | Method of forming a package assembly A method of forming a package assembly (10) including a package (12) that encapsulates an electronic die. A leadframe (30) has edge rails (32), and the die is disposed on the leadframe. The package is formed around the die to encapsulate it, and the leadf... | 08/26/1997 |
| 5656844 | Semiconductor-on-insulator transistor having a doping profile for fully-depleted operation A semiconductor-on-insulator transistor (10) has a channel region (30) in a semiconductor film (16) under a gate insulating layer (26). The channel region has a top dopant concentration NT at a top surface (32) of the film that is significantly... | 08/12/1997 |
| 5646072 | Electronic sensor assembly having metal interconnections isolated from adverse media A pressure sensor (32) having a transducer (34) disposed on a top surface of an active die (38). The transducer has a doped region (42), the active die is disposed on a mounting substrate (70), and an interconnect opening (48) is disposed at an edge (90) ... | 07/08/1997 |
| 5639683 | Structure and method for intergrating microwave components on a substrate A component integration structure (10) for a microwave system includes a silicon substrate (12) having a resistivity greater than about 2,000 ohm-cm. A first die (14) is disposed on the silicon substrate, and a first passive element (20) is disposed on th... | 06/17/1997 |
| 5631192 | Semiconductor device on an opposed leadframe and method for making A semiconductor device (10) is formed from a single leadframe (11) by aligning two electronic components (22,24) relative to each other. The leadframe (11) has two bonding regions (30,31), which are offset from each other, and interconnect bars (13) which... | 05/20/1997 |
| 5631175 | Method for fabricating an elevated-gate field effect transistor A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative... | 05/20/1997 |
| 5629536 | High voltage current limiter and method for making A current limiter (15) is formed between a silicon substrate (10) and a source region (17) by a channel implant region (20). The channel implant region (20) is not modulated by a gate structure so the maximum voltage that can flow between the silicon subs... | 05/13/1997 |
| 5623159 | Integrated circuit isolation structure for suppressing high-frequency cross-talk An improved isolation structure for a semiconductor device includes a p-type semiconductor substrate (12) with a p-type well (28) disposed in the substrate (12). A continuous plurality of n-type regions (14, 16, 26) is disposed around the p-type well (28)... | 04/22/1997 |
| 5604700 | Non-volatile memory cell having a single polysilicon gate A non-volatile memory cell (10) is provided employing two transistors (11, 12) connected in series. A floating gate structure (13), formed with a single polysilicon deposition, is shared by each transistor (11, 12) to store the logic condition of the memo... | 02/18/1997 |
| 5604160 | Method for packaging semiconductor devices A cap wafer (10) is used to package semiconductor devices on a device wafer (30). Successive etching processes form a plurality of partially etched cavities (27) extending from a front surface (11) of the cap wafer (10) into the cap wafer (10). The patter... | 02/18/1997 |
| 5602491 | Integrated circuit testing board having constrained thermal expansion characteristics A board (10) for testing an integrated circuit disposed on a semiconductor wafer. The board contains a plurality of substantially parallel signal layers (14) and power planes (16) that are supported and electrically isolated by a dielectric material (12).... | 02/11/1997 |
| 5591676 | Method of making a semiconductor device having a low permittivity dielectric A semiconductor device having electronic circuitry formed in a semiconductor substrate (11) and separated from an overlying metal interconnect layer (18,18') using a fluorinated polymer dielectric (14,14') . The fluorinated polymer layer (14,14') may be f... | 01/07/1997 |
| 5585281 | Process and apparatus for forming and testing semiconductor package leads A method of forming leads and providing a final test of a semiconductor package including an electronic circuit therein, the package having unformed leads. A forming and testing station is provided including a support for receiving the package, and dies m... | 12/17/1996 |
| 5583355 | Self-aligned FET having etched ohmic contacts A III-V semiconductor FET (10, 30, 40) having etched ohmic contacts (19, 20, 36, 37, 43, 44). A gate (16) of the FET (10, 30, 40) is formed in contact with a surface of a III-V substrate (11). An ohmic contact (19, 20, 36, 37, 43, 44) is created to includ... | 12/10/1996 |
| 5578167 | Substrate holder and method of use The etching of a thin substrate (23) is performed using a holder (10). The holder (10) has a base (11) that has a cavity (20). The cavity (20) is pressurized to compensate for the pressure and stress that is applied to the substrate (23) by an etchant sol... | 11/26/1996 |
| 5576563 | Chemical probe field effect transistor for measuring the surface potential of a gate electrode in response to chemical exposure A chemical probe field effect transistor (10) for measuring surface potential as a function of temperature and used for chemical sensing. Source and drain regions (14, 16) in a semiconductor substrate (12) define a channel region (34). A gate insulating l... | 11/19/1996 |
| 5574621 | Integrated circuit capacitor having a conductive trench A capacitor (58) for an integrated circuit having a conductive trench (50), disposed below a bottom electrode layer (52), that electrically connects the bottom electrode layer to a semiconductor substrate (14, 16). The conductive trench eliminates the nee... | 11/12/1996 |
| 5567649 | Method of forming a conductive diffusion barrier A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13,... | 10/22/1996 |
| 5559359 | Microwave integrated circuit passive element structure and method for reducing signal propagation losses A passive element structure and method for a microwave integrated circuit reduces signal propagation losses. In one approach, a passive element (10) has an insulating layer (12) overlying a silicon substrate (14). A metal layer (16) comprising a signal li... | 09/24/1996 |
| 5553566 | Method of eliminating dislocations and lowering lattice strain for highly doped N+ substrates A method for fabricating semiconductor substrates with resistivity below 0.02 ohm-cm is provided. This low resistivity is achieved by doping a silicon melt with a phosphorus concentrations above 1×1018. The silicon melt is also doped with a ge... | 09/10/1996 |
| 5551304 | Method for setting sensing polarity of a sensor device A method for setting the sensing polarity of a sensor device (10) uses a switching bridge (22) having a wheatstone bridge configuration that is coupled to a sensing element (20) such that the polarity of the sensor device can be set by creating two electr... | 09/03/1996 |
| 5545912 | Electronic device enclosure including a conductive cap and substrate An enclosure (8) for an electronic device (26) such as, for example, an accelerometer. The enclosure (8) includes a conductive semiconductor substrate (12) underlying the electronic device (26), a conductive cap (16) overlying the electronic device (26), ... | 08/13/1996 |
| 5535510 | Plastic encapsulated microelectronic device and method An encapsulated microelectronic device (100) including a base (101) and a semiconductor device (305) having a top and a bottom. The bottom is attached to the base (101). The semiconductor device (105) has a thickness in the range from one-fourth to three-... | 07/16/1996 |
| 5528069 | Sensing transducer using a Schottky junction and having an increased output signal voltage A sensing transducer (10,30) and a method therefor uses a Schottky junction (12) having a conductive layer (16) disposed on a semiconductor substrate (14). The conductive layer (16) is generally formed from the reaction of a metal with a portion of the se... | 06/18/1996 |
| 5523629 | Plastic encapsulated microelectronic device An encapsulated microelectronic device (100 ) including a base (101) and a semiconductor device (305) having a top and a bottom. The bottom is attached to the base (101). The semiconductor device (105) has a thickness in the range from one-fourth to three... | 06/04/1996 |
| 5509041 | X-ray lithography method for irradiating an object to form a pattern thereon An x-ray lithography method for irradiating an object (14) to form a pattern thereon uses an x-ray mask (10) having a membrane (18). The membrane (18) has an open membrane surface (26), and x-ray radiation (16) is passed through the open membrane surface ... | 04/16/1996 |
| 5508539 | Elevated-gate field effect transistor structure and fabrication method A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative... | 04/16/1996 |
| 5500912 | Holographic optical isolator utilizing opto-electronic transmitter and receiver disposed in a package An opto-isolator (10) increases optical efficiency by using holographic elements (22,24,26) to direct a beam of light (34) through an optical waveguide (20). An opto-electronic transmitter (12) and receiver (16) are connected to the waveguide to be in ali... | 03/19/1996 |
| 5461260 | Semiconductor device interconnect layout structure for reducing premature electromigration failure due to high localized current density In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is co... | 10/24/1995 |
| 5438877 | Pressure sensor package for reducing stress-induced measurement error A pressure sensor package (10) has a sensor body (12) for containing a pressure sensor. An elongated stem (14) has a first end connected to the sensor body (12), and a connector (24, 26) is disposed on a second end of the stem (14) for fixedly mounting th... | 08/08/1995 |
