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| Number | Title | Issue Date |
| 6020264 | Method and apparatus for in-line oxide thickness determination in chemical-mechanical polishing In-line thickness measurement of a dielectric film layer on a surface of a workpiece subsequent to a polishing on a chemical-mechanical polishing machine in a polishing slurry is disclosed. The workpiece includes a given level of back-end-of-line (BEOL) s... | 02/01/2000 |
| 5821542 | Particle beam imaging system having hollow beam illumination An charged particle beam imaging system reduces aberrations affecting resolution at the workpiece where the aberrations are caused by interactions between the charged particles in the beam. The average distance between the particles at a crossover image i... | 10/13/1998 |
| 5768556 | Method and apparatus for identifying dependencies within a register An apparatus for use with a computer system for identifying dependencies within a register, which dependencies are established by a succession of instructions for the computer system. The register includes a plurality of cells which may be in a hierarchic... | 06/16/1998 |
| 5760611 | Function generator for programmable gate array A programmable logic circuit provides a variety of logic functions including AND/NAND, OR/NOR, XOR/XNOR. Selection of logic function is provided by controlling inputs, using programmable inverters and programmable multiplexers. The logic circuit can be in... | 06/02/1998 |
| 5719889 | Programmable parity checking and comparison circuit A programmable parity circuit for a memory array includes at least one programmably selectable set of inputs arranged such that the circuit can be programmably configured to perform odd or even parity operations for data stored or to be stored in the memo... | 02/17/1998 |
| 5719505 | Reduced power PLA A reduced power programmable logic array is disclosed. The circuit includes an AND array, coupled through product term lines to an output OR array. Pull-up devices in the OR array are gated to one of the active product term lines. Also disclosed is method... | 02/17/1998 |
| 5715064 | Step and repeat apparatus having enhanced accuracy and increased throughput A multi-station Step and Repeat Apparatus (Stepper) for imaging semiconductor wafers. The stepper has at least 2 stations, at least one of which is for imaging. The second station may be used for image field characterization, or image defect correction, o... | 02/03/1998 |
| 5712790 | Method of power reduction in pla's A reduced power programmable logic array is disclosed. The circuit includes an AND array, coupled through product term lines to an output OR array. Pull-up devices in the OR array are gated to one of the active product term lines. Also disclosed is method... | 01/27/1998 |
| 5689127 | Vertical double-gate field effect transistor A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation r... | 11/18/1997 |
| 5674409 | Nanolithographic method of forming fine lines A nanolithographic method for forming fine features is disclosed. A carrier layer, such as a photoresist, is deposited on a substrate. A relatively large pattern is imposed on the carrier layer by means of conventional photolithographic methods. The carri... | 10/07/1997 |
| 5668492 | Integrated circuit clocking technique and circuit therefor A globally distributed system clock is received and selectively gated by local clock generators responsive to global control signals. The local clock generators, which are located proximately to sequential circuits having serial scan paths, produce scan a... | 09/16/1997 |
| 5646053 | Method and structure for front-side gettering of silicon-on-insulator substrates A method of gettering an SOI wafer from the front side of the wafer includes depositing a gettering layer, such as polysilicon, on the SOI layer and annealing the SOI wafer with the gettering layer in place. A polish stop structure, which can be deposited... | 07/08/1997 |
| 5635861 | Off chip driver circuit Disclosed is an improved push-pull off-chip driver circuit. The circuit includes a push-pull amplifier including a pull-up transistor and a pull-down transistor, each provided with independent inputs and connected at the output node. The input to the pull... | 06/03/1997 |
| 5511016 | Method for store rounding and circuit therefor A method and circuit for store rounding a number wherein the guard bit and least significant bit of the number are selectively exchanged depending on the IEEE rounding mode to simplify the decision-making circuit. Zero detection logic is performed on the ... | 04/23/1996 |
| 5424254 | Process for recovering bare semiconductor chips from plastic packaged modules by thermal shock The method of the present invention is particularly directed to plastic packaged modules of the type wherein the contact zones of the chip are connected by wire-bonding to lead conductors and wherein the chip is molded in etch resistant resins. The openin... | 06/13/1995 |
