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| Number | Title | Issue Date |
| 7084696 | Circuits associated with fusible elements for establishing and detecting of the states of those elements A state detection circuit for a fusible element includes a differential sensing circuit that compares voltage at a detection point in a path containing the fusible element with that at a reference point in a path establishing a non-zero reference voltage. The paths ... | 08/01/2006 |
| 7053659 | CMOS high speed level shifting differential receiver Rapid switching is provided by a circuit that controls the current passing through a chain of CMOS devices arranged in a series circuit. A node output terminal to the circuit is provided intermediate the chain to control the partially conductive state of two other C... | 05/30/2006 |
| 7010735 | Stuck-at fault scan chain diagnostic method While data cannot be transmitted down a scan chain through a stuck-at fault location, data in properly operating latches downstream of the stuck-at fault location can be shifted down the chain. By varying operating parameters, such as power supply and reference volt... | 03/07/2006 |
| 6968489 | Pseudo random optimized built-in self-test Flat pseudo random test patterns are provided in combination with weighted pseudo random test patterns so that the weight applied to every latch in a LSSD shift register (SR) chain can be changed on every cycle. This enables integration of on-chip weighted pattern g... | 11/22/2005 |
| 6952739 | Method and device for parameter independent buffer underrun prevention A method and device for parameter independent buffer underrun prevention in a data communication system includes a buffer for compensating for a difference in the rate of flow of data having a write port and a read port. After a commencement of writing data into the... | 10/04/2005 |
| 6891528 | Interchangeable keyboard with self defining keys Each keyboard key is marked with a self-defining indicator. A matrix of key sensing circuits for the keyboard are configured to detect this indicator when the keys are depressed and provide an output to a keyboard controller which in turn provides key signals to the... | 05/10/2005 |
| 6816990 | VLSI chip test power reduction LBIST and weighted LBIST tests are performed simultaneously on different portions of the tested object. This new test methodology and design change achieves the same test coverage and test time as the traditional test strategy with dramatic power reduction during te... | 11/09/2004 |
| 6192349 | Smart card mechanism and method for obtaining electronic tickets for goods services over an open communications link A smart card, (a type of credit card containing storage capacity and processing ability preferably in the form of a microprocessor), is used to store an electronic ticket provided from the service provider's computer system to the customer's computer over... | 02/20/2001 |
| 6188703 | Multiplexer for multiple media streams A multimedia terminal having a host processor, an audio and video encoder, a system time clock, and a multiplexer is provided. The encoders input elementary stream of data into the multiplexer. The multiplexer is comprised of a mux processor, a FIFO which... | 02/13/2001 |
| 5909262 | Semiconductor device and driving method for semiconductor device A liquid crystal display cell includes a voltage amplification function therein for driving the cell with an AC voltage. The cell includes gate lines running in a first direction, a source line running in a second direction different from the first direct... | 06/01/1999 |
| 5821818 | Phase locked loop ciruit for a liquid crystal display This single voltage controlled oscillator for a PLL circuit has two control loops: a low noise ration is maintained by a main loop; while a wide frequency capture range is ensured by a sub-loop controlled by a one-chip microcomputer. The main control loop... | 10/13/1998 |
| 5822604 | Method of optimizing recognition of collective data movement in a parallel distributed system To optimize collective data movement recognition in a parallel distributed system a data movement set is formed into a data structure where access regularity is efficiently used with respect to problems, and processor expression independent of the number ... | 10/13/1998 |
| 5818424 | Rod shaped device and data acquisition apparatus for determining the position and orientation of an object in space A rod-shaped device for spatial data acquisition includes a shank (1) with at least two separated, substantially identical marker field structures (3, 4) on the surface of the shank (1). The marker field structures (3, 4) are resolvable for imaging purpos... | 10/06/1998 |
| 5808302 | Fine positioning apparatus with atomic resolution A fine-positioning apparatus for a scanning probe microscope includes magnetic solenoid actuators for each of the x, y and z scanning axes of the microscope. The sample is mounted on the coil of one of the actuators for movement of the sample in the z dir... | 09/15/1998 |
| 5797122 | Method and system using separate context and constituent probabilities for speech recognition in languages with compound words In a method and system for speech recognition in the case of languages containing compound words only components of compound words are stored in a language model. Only these components are handled in the vocabulary. In recognizing possible compound words separ... | 08/18/1998 |
| 5787196 | Method and apparatus for splitting connected characters into component characters Image processing apparatus is disclosed for splitting, for subsequent storage or processing by OCR apparatus, character images in digital form comprising connected characters, the image processing apparatus extracts an image skeleton from an input image a... | 07/28/1998 |
| 5780727 | Electromechanical transducer A field effect transistor and a piezoelectric sensor are positioned between layers of silicon and aluminum to function as a bimetallic electromechanical transducer. The transducer can be used in atomic force microscopy or as an actuator, a chemical sensor... | 07/14/1998 |
| 5705920 | Power supply apparatus A power supply apparatus which stabilizes the output by feeding it back is provided which suppresses variations of the output for abrupt variations of the input. The power supply apparatus comprises output sensing means for sensing output current and outp... | 01/06/1998 |
| 4783657 | Processor intercommunication network In a processor intercommunication network, every pair of processors is connected by a separate path for carrying multi-bit orders so that in an N processor multiprocessing system there are N-1 bidirectional communication paths to and from each of the N pr... | 11/08/1988 |
| 4627017 | Address range determination An (M plus K)-digit accessed address is checked to see if it may fall within a range of addresses g defined by the address at one end of the range plus a variable range of addresses (g). The checking is done in a single step in a comparison of the K lowes... | 12/02/1986 |
| 4618292 | Controls for semiconductor wafer orientor This specification deals with electro-optic controls for stopping and orienting of a semiconductor wafer being transported along a track on an air film. At one or more locations along the track the characteristics of the air film are changed by electronic... | 10/21/1986 |
| 4613936 | Centralized generation of data transfer acknowledge pulses for microprocessors Centralized generation of data transfer acknowledgment (DTACK) pulses is provided instead of providing each of the devices with their own DTACK pulse generation facilities. In this centralized DTACK generator, a number of gating circuits are gated on at d... | 09/23/1986 |
| 4611279 | DMA asynchronous mode clock stretch An adaptively stretched clock input feature is provided on a natively synchronous DMAC device to make it support data transfers in an asynchronous bus environment. This feature effects adjustment of the DMAC transfer strobe access window as a function of ... | 09/09/1986 |
| 4584682 | Reconfigurable memory using both address permutation and spare memory elements An array substitution scheme is used to substitute a spare chip for a faulty chip when a UE condition results from an alignment of two errors in bit positions accessed through the same decoder while the bit permutation apparatus is used to misalign fault ... | 04/22/1986 |
| 4584681 | Memory correction scheme using spare arrays Spare chips are employed together with a replacement algorithm to replace chips in memory array when failure is generally more extensive then unrelated cell fails in the memory chips. That is, substitution will be made if an error condition is a result of... | 04/22/1986 |
| 4581563 | Variable format controls CRT raster Feedback loops monitor the vertical and horizontal deflection yoke drive voltages of the CRT and separately compare each potential with a voltage which represents full screen deflection. Error voltage resulting from these comparisons adjust the power supp... | 04/08/1986 |
| 4556977 | Decoding of BCH double error correction - triple error detection (DEC-TED) codes Decoding of BCH multiple error correction code codewords with as a primitive element of the finite field GF (2m) is accomplished by generating syndrome subvectors S1 from all column m-tuple k positions and s... | 12/03/1985 |
| 4547710 | Cathode ray tube display horizontal deflection system with delay compensation The initiation of the flyback interval of a variable format CRT display system is controlled by a frequency independent closed loop compensation circuit. The termination point of a sawtooth pulse, which is initiated at the start of the horizontal sync for... | 10/15/1985 |
| 4534029 | Fault alignment control system and circuits This permutation circuit can be considered to be a multi-bit adder without a carry. In one embodiment it takes the form of m address bits being fed to m+y 2-way exclusive OR gates with m+y permutation bits to generate m+y input bits accessing a decoder wi... | 08/06/1985 |
| 4530053 | DMA multimode transfer controls Circuitry is provided to be used in association with a single transfer mode DMAC device to enable a programmer to control the number of bytes transferred during a DMA transfer cycle. The circuitry receives a coded mode control message from the microproces... | 07/16/1985 |
| 4513418 | Simultaneous self-testing system The LSSD scan paths on a number of logic circuit chips are modified and connected together in series to simultaneously serve as a random signal generator and data compression circuit to perform random stimuli signature generation.... | 04/23/1985 |
| 4509172 | Double error correction - triple error detection code A code is generated using BCH coding theory which corrects double bit failures and detects triple failures and packaging errors. The code is a shortened code in which both data and check bit columns have been removed from the parity check matrix. A decodi... | 04/02/1985 |
| 4506364 | Memory address permutation apparatus Swapping of bits between different words of a memory is accomplished by a single permutation means. The single permutation means generates actual address bits for all the bit positions in a memory word. These actual address bits are in a local store. Each... | 03/19/1985 |
| 4506158 | Dual mode spectrometer test station A new spectrometer station for semiconductor wafers is provided that permits operation in both the reflective and absorption modes either simultaneously or sequentially while the wafer is in a horizontal position. The wafer is positioned in the station on... | 03/19/1985 |
| 4503537 | Parallel path self-testing system The LSSD scan paths of each logic circuit chip on a circuit module are connected to additional test circuit chips on the same module. The test chips contain a random signal generator and data compression circuit to perform random stimuli signature generat... | 03/05/1985 |
| 4489403 | Fault alignment control system and circuits The makeup of memory words is controlled by a memory address permutator that permits up to 2n ! input bit combinations. The particular combinations used in any decoder is dependent on the particular application. The new permutator also permits ... | 12/18/1984 |
| 4489272 | Test circuit for turn-on and turn-off delay measurements A test circuit that is particularly suitable for inclusion on an LSI chip when testing a new technology or process. The circuit will enable accurate determination of the effects of loading on the turn-on and turn-off delays of one or more logic circuits o... | 12/18/1984 |
| 4485471 | Method of memory reconfiguration for fault tolerant memory Swapping of bits between different words of a memory is accomplished by reference to data on bad bits in the memory. This data controls address inputs to each bit in a memory word so that any word with multiple uncorrectable errors is changed to a correct... | 11/27/1984 |
| 4476734 | Wet needle sampler for use with a gas chromatograph The flushing of the syringe with a side port is performed by introducing a liquid solvent through the side port while the plunger is retracted from the barrel. At the completion of the flushing operation the plunger is fully inserted into the barrel expel... | 10/16/1984 |
| 4466099 | Information system using error syndrome for special control Special control within a data processing system is signalled by a predetermined unique combination of data and error correcting code (ECC) bits. The predetermined combination, received from a source 1, is one which normally is decoded to indicate the pres... | 08/14/1984 |
