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| Number | Title | Issue Date |
| 8055989 | Boot security using embedded counters The present disclosure provides a system for providing a security and method of providing an enhanced security booting environment. The system and method includes a basic input/output system (BIOS) stored in memory. The system and method also includes a counter embe... | 11/08/2011 |
| 8054980 | Apparatus and method for rendering audio information to virtualize speakers in an audio system An audio processor, apparatus, and method use physical speakers to emulate one or more additional speakers. The physical speakers produce sounds that, from a listener's perspective, appear to come from at least one direction where a physical speaker is not present. ... | 11/08/2011 |
| 8054787 | Apparatus and method for enhanced adaptive channel selection and subframe allocation in a communication system A first base station is adjacent to one or more second base stations, and the second base stations are adjacent to one or more third base stations. One or more frequency channels or subframes used by the third base stations are identified by the second base stations... | 11/08/2011 |
| 8054141 | Method and circuit for cancelling out comparator-delay in the relaxation oscillator A relaxation oscillator includes a capacitor connected to a comparator input, current sources switched to supply power to the capacitor based on an output of the comparator, and a duplicate integrator shifting a voltage on the capacitor to offset a propagation delay... | 11/08/2011 |
| 8040626 | High-rate transition control code for magnetic recording channels A method and apparatus for reducing noise in a communication signal is provided. The method includes converting raw channel data from the communication signal to a sequence of transition code symbols, each symbol having a plurality of bits, each bit having a positio... | 10/18/2011 |
| 8019035 | Noise shaped interpolator and decimator apparatus and method Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to... | 09/13/2011 |
| 8018036 | Ultra-thin quad flat no-lead (QFN) package An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electricall... | 09/13/2011 |
| 7995217 | High-resolution encoder array A position sensing apparatus and method, motion control system, and integrated circuit are provided that include a plurality of sensors and a tracking processor. The plurality of sensors includes a linear array of sensors that sense a plurality of features of an obj... | 08/09/2011 |
| 7984467 | Method and system for providing an electronic program guide In a method for providing a program guide in a program receiver, program schedule data is received, wherein the program schedule data associates programs with time slots on a particular channel of a plurality of channels. For a first time slot of a virtual channel, ... | 07/19/2011 |
| 7956345 | CNT devices, low-temperature fabrication of CNT and CNT photo-resists A method is provided for growth of carbon nanotube (CNT) synthesis at a low temperature. The method includes preparing a catalyst by placing the catalyst between two metal layers of high chemical potential on a substrate, depositing such placed catalyst on a surface... | 06/07/2011 |
| 7954017 | Multiple embedded memories and testing components for the same A method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is us... | 05/31/2011 |
| 7948114 | Apparatus and method for providing a power switch array with adjustable current rating power switches An apparatus and method are disclosed for providing a power switch array with adjustable current rating power switches. A plurality of current rating power switches is provided that connects a power supply unit to a plurality of device ports. A power switch array co... | 05/24/2011 |
| 7929649 | Analog/digital carrier differentiation in digital cable receivers A communication signal carrier on a communication channel in a digital cable receiver can be characterized as analog without exhaustively attempting to determine a symbol rate or modulation scheme of a digital carrier. The signal level in the channel is observed at ... | 04/19/2011 |
| 7927424 | Padded clamp ring with edge exclusion for deposition of thick AlCu/AlSiCu/Cu metal alloy layers A substrate clamp ring has an edge exclusion lip with a variable bottom surface. At least a portion of that bottom surface has a height above the substrate contact level selected to minimize accumulation over time of deposited aluminum-copper alloy across lower port... | 04/19/2011 |
| 7924937 | Resonant power converter for radio frequency transmission and method A resonant power converter for ultra-efficient radio frequency transmission and associated methods. In one exemplary embodiment, the invention is digitally actuated and uses a combination of a noise-shaped encoder, a charging switch, and a high-Q resonator coupled t... | 04/12/2011 |
| 7924839 | Mechanism to reduce lookup latency in a pipelined hardware implementation of a trie-based IP lookup algorithm A series of hardware pipeline units each processing a stride during prefix search operations on a multi-bit trie includes, within at least one pipeline unit other than the last pipeline unit, a mechanism for retiring search results from the respective pipeline unit ... | 04/12/2011 |
| 7919361 | Semiconductor package with position member The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position membe... | 04/05/2011 |
| 7904905 | System and method for efficiently executing single program multiple data (SPMD) programs A system and method is disclosed for efficiently executing single program multiple data (SPMD) programs in a microprocessor. A micro single instruction multiple data (SIMD) unit is located within the microprocessor. A job buffer that is coupled to the micro SIMD uni... | 03/08/2011 |
| 7895213 | Method and system for providing cascaded trie-based network packet search engines A method for providing cascaded trie-based network packet search engines is provided. A search command is received at one of the network packet search engines. The search command comprises a specific search key. A determination of a longest prefix match based on the... | 02/22/2011 |
| 7873515 | System and method for error reconstruction of streaming audio information A method includes receiving a sequence of frames containing audio information and determining that a frame is missing in the sequence of frames. The method also includes comparing the frame that precedes the missing frame to the received frames to identify a selecte... | 01/18/2011 |
| 7873510 | Adaptive rate control algorithm for low complexity AAC encoding A system and method for adaptive rate control in audio processing is provided. The process could include receiving uncompressed audio data from an input and generating MDCT spectrum for each frame of the uncompressed audio data using a filterbank. The process could ... | 01/18/2011 |
| 7844167 | System and apparatus for digital audio/video decoder splitting signal into component data streams for rendering at least two video signals The present invention provides a system and an apparatus for a digital audio/video decoder comprising a file reader capable of obtaining an encoded audio/video data stream from a data source, a navigator that instructs the file reader to obtain the encoded audio/vid... | 11/30/2010 |
| 7840761 | Apparatus and method for supporting execution of prefetch threads A processor executes one or more prefetch threads and one or more main computing threads. Each prefetch thread executes instructions ahead of a main computing thread to retrieve data for the main computing thread, such as data that the main computing thread may use ... | 11/23/2010 |
| 7836279 | Method and system for supporting software pipelining using a shifting register queue A system for supporting software pipelining using a shifting register queue is provided. The system includes a register file that comprises a plurality of registers. The register file is operable to receive a shift mask signal and a shift signal and to identify a sh... | 11/16/2010 |
| 7825959 | System and method for flicker DC offset detection and correction The present disclosure provides a method for detecting flicker DC voltage offset. The method includes receiving an output signal of an image sensor, the output signal comprising a reference signal and an image signal, and generating a combined signal by combining th... | 11/02/2010 |
| 7825917 | Apparatus and method for adjusting a display using an integrated ambient light sensor An apparatus includes a display panel capable of displaying content. The apparatus also includes a light sensor having an integrated circuit and a photo-sensitive device. The photo-sensitive device is capable of measuring an amount of ambient light. The integrated c... | 11/02/2010 |
| 7816182 | Simplified multichip packaging and package design A multichip integrated circuit apparatus includes first and second integrated circuit die mounted on opposite sides of a leadframe die paddle, with at least one of the integrated circuit die extending further toward the leads than does the die paddle. With this arra... | 10/19/2010 |
| 7802255 | Thread execution scheduler for multi-processing system and method A processing system includes a plurality of processors capable of executing a plurality of threads and supporting at least one of hardware context switching and software context switching. The processing system also includes at least one hardware scheduler capable o... | 09/21/2010 |
| 7802172 | Variable-rate low-density parity check codes with constant blocklength Low density parity check (LDPC) codes (LDPCCs) have an identical code blocklength and different code rates. At least one of the rows of a higher-rate LDPC matrix is obtained by combining a plurality of rows of a lower-rate LDPC matrix with the identical code blockle... | 09/21/2010 |
| 7800324 | Continuous mode velocity control of voice coil motor A method of controlling the velocity of a voice coil motor (VCM), including sensing a voltage difference between the VCM and a sense resistor and driving a velocity control loop (VCL) based on the voltage difference. There is also a control loop circuit, including a... | 09/21/2010 |
| 7800322 | Isolation circuit for DC power sources The electrical isolation circuit of the present disclosure includes a switch coupled between the DC power source and the electrical application and a comparator for controlling the switch by receiving inputs from the DC power source and the electrical application. T... | 09/21/2010 |
| RE41728 | High linearity, low power voltage controlled resistor A number of voltage-controlled resistance cells, each formed by a transistor with a biasing capacitor connected between the gate and source and an associated controller coupled to the capacitor to maintain a steady charge on the biasing capacitor and keep the gate-s... | 09/21/2010 |
| 7786582 | System for providing a redistribution metal layer in an integrated circuit A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation i... | 08/31/2010 |
| 7782853 | Apparatus and method of using fully configurable memory, multi-stage pipeline logic and an embedded processor to implement multi-bit trie algorithmic network search engine A multi-bit trie network search engine is implemented by a number of pipeline logic units corresponding to the number of longest-prefix strides and a set of memory blocks for holding prefix tables. Each pipeline logic unit is limited to one memory access, and the te... | 08/24/2010 |
| 7779240 | System and method for reducing power consumption in a data processor having a clustered architecture There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, ... | 08/17/2010 |
| 7779236 | Symbolic store-load bypass The invention provides a method and system for operating a pipelined microprocessor more quickly, by detecting instructions that load from identical memory locations as were recently stored to, without having to actually compute the referenced external memory addres... | 08/17/2010 |
| 7778480 | Block filtering system for reducing artifacts and method A method includes identifying a pair of image data blocks separated by a boundary. The image data blocks include image information defining multiple pixels in at least one image. The method also includes identifying at least one filter length based on edge contents ... | 08/17/2010 |
| 7774767 | System and method for compiler interprocedural optimization having support for object files in libraries A method includes extracting at least one object file from a library of object files. The method also includes identifying an interprocedural optimization associated with a plurality of object files. The plurality of object files includes the at least one extracted ... | 08/10/2010 |
| 7774574 | Prototyping integrated systems A prototype system having an integrated circuit including an on-chip processor and an on-chip router connected to off-chip resources via an interface. A request directing unit on the chip receives memory access requests and directs them in accordance with either one... | 08/10/2010 |
| 7757066 | System and method for executing variable latency load operations in a date processor There is disclosed a data processor that executes variable latency load operations using bypass circuitry that allows load word operations to avoid stalls caused by shifting circuitry. The processor comprises: 1) an instruction execution pipeline comprising N proces... | 07/13/2010 |
