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| Number | Title | Issue Date |
| 8178901 | Integrated circuit assembly with passive integration substrate for power and ground line routing on top of an integrated circuit chip An integrated circuit assembly (ICA) comprises: a digital and/or analog integrated circuit (S1) having a core with input and/or output pins and at least one power supply connection pad (PP) and one ground connection pad (GP) connected to a chosen one of the i... | 05/15/2012 |
| 8098721 | Reception of a signal transmitted over a transmission link comprising coded channels A method to receive a signal transmitted over a transmission link comprising coded channels, the method comprising: —equalization operations (110-116) to compensate for signal distortion introduced by the transmission link in a signal burst, and—bl... | 01/17/2012 |
| 8081939 | Correlation-driven adaptation of frequency control for a RF receiver device A frequency-control unit is used for controlling an external controllable reference-frequency source. The frequency-control unit includes a filter unit with a controllable filter parameter, which is configured to derive, using the filter parameter, from a frequency-... | 12/20/2011 |
| 8081500 | Method for mitigating imprint in a ferroelectric memory An array of ferroelectric memory cells that allows imprint mitigation includes ferroelectric memory cells respectively coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; ... | 12/20/2011 |
| 8073045 | Method and a system for generating an adaptive slicer threshold An adaptive slicer threshold is derived from averages of maximum and minimum values of the received signal, the method comprising the steps of: —averaging (86) several detected maximum values and averaging several detected minimum values, and —calculating... | 12/06/2011 |
| 8054055 | Fully integrated on-chip low dropout voltage regulator A low dropout voltage regulator (LDO) includes a bias voltage generator, a differential error amplifier, an output driver, a controlled active load, a Double Ended Cascode Miller compensation block. The bias voltage generator produces a plurality of bias voltages. T... | 11/08/2011 |
| 8048000 | Patient weight and ankle displacement correlation device A device for correlating trend data with respect to a patient's weight ankle displacement can identify conditions indicative of congestive heart failure. A weight scale or similar device coupled with imaging mechanism operable to measure ankle displacement collects ... | 11/01/2011 |
| 8045986 | Cell selection device for wireless communication equipment A cell selection device (D) is dedicated to a piece of wireless communication equipment (MS) arranged to establish radio communications with a radio communication network comprising radio communication cells and to receive data representative of the cell environment... | 10/25/2011 |
| 8044756 | Programmable inductor The present invention provides a programmable integrated inductor having a compact design, having a dual turn and a parallel programmable impedance. In particular, the impedance value of the programmable changes, like a variable, programmable, as its range may be se... | 10/25/2011 |
| 8044684 | Input and output buffer including a dynamic driver reference generator A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level shifter to generate level shifted signals based, in part, on the dyn... | 10/25/2011 |
| 8040172 | Logic level converter A logic level converter includes two first electronic switches coupled in a bi-stable flip-flop arrangement having at least one output line, and a forcing circuitry including two second electronic switches to force switching of the first electronic switches in the f... | 10/18/2011 |
| 8019985 | Data-processing arrangement for updating code in an auxiliary processor memory A data-processing arrangement includes a main processor and an auxiliary processor. A system-program code causes the main processor to write an application-program code into a shared memory. The system-program code further causes the main processor to write an addre... | 09/13/2011 |
| 8015562 | Process for managing virtual machines in a physical processing machine, corresponding processor system and computer program product therefor A process for managing virtual machines in a physical machine includes the generation of virtual machines and executing operating systems in the virtual machines on top of the physical machine. A virtual machine monitoring function includes the operations of running... | 09/06/2011 |
| 8014112 | Integrated circuit with device for protection against electrostatic discharges An integrated circuit includes a substrate of semiconductive material, a first circuit environment made from the substrate which includes an output terminal and a first pair of power supply terminals for receiving a first power supply voltage applicable between the ... | 09/06/2011 |
| 8005159 | Methods for channel estimation in the presence of transmit beamforming The present invention relates to a method for estimating a propagation channel in the presence of transmit beam-forming within a receiver, accounting for the structure of two logical channels referred as to a common channel and a dedicated physical channel (CPICH, D... | 08/23/2011 |
| 8000051 | Method for recovering a position and clock period from an input digital signal A method for recovering a position and clock period from an input bi-phase encoded digital signal such as an SPDIF signal counts the intervals between phase changes of the input digital signal to derive the longest interval between the phase changes. The longest int... | 08/16/2011 |
| 7999597 | Circuit adjustable after packaging having a voltage limiter and method of adjusting same A circuit adjustable after packaging includes a functional circuit supplied with a power potential and a reference potential and has at least one parameter adjustable by programming at least one programmable element and a circuit to program the programmable element ... | 08/16/2011 |
| 7998356 | Optical integrated device manufacturing process The invention relates to a process for manufacturing an integrated optical device. The method involves forming a silicon dioxide multilayer structure on a silicon substrate containing, in a first region a core layer of a waveguide of the optical device. The core inc... | 08/16/2011 |
| 7984365 | Turbo decoder with stake heritage for data block redundant version decoding An iterative decoding device for a communication receiver includes a decoder for decoding received encoded data blocks by a next iteration initialization, a controller to choose one of the first and second hard decision bits in order for the validity of a CRC field,... | 07/19/2011 |
| 7983625 | Notch filter and apparatus for receiving and transmitting radio-frequency signals incorporating same A notch filter suitable for attenuating certain frequencies of a radio-frequency signal includes an input for receiving the radio-frequency signal and an output for the output of a portion of the radio-frequency signal, first and second capacitive means, at least on... | 07/19/2011 |
| 7978644 | Method of fair scheduling channel access in a wireless network A method of fair scheduling for channel access in a wireless network comprising a plurality of nodes including a first node and at least one second node is described, the method comprising the steps of: arranging (RICP) a packet to... | 07/12/2011 |
| 7966432 | Data processing device adaptable to variable external memory size and endianess A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising ... | 06/21/2011 |
| 7962837 | Technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while a... | 06/14/2011 |
| 7949313 | Direct conversion device with compensation means for a transmission path of a wireless communication equipment A conversion device (CD) is dedicated to conversion of baseband analog I/Q input signals into RF signals in a transmitting path of a wireless communication equipment. This device (CD) comprises i) first (PP1) and second (PP2) processing paths each comp... | 05/24/2011 |
| 7925286 | Method, a program and a module to estimate a doppler maximum frequency and an oscillator frequency offset, receiver including the module A method of estimating a Doppler maximum frequency fd and/or a local oscillator frequency offset f0, the method comprising the steps of: computing a power density spectrum of a received radio signal over a whole frequency range, scanning the co... | 04/12/2011 |
| 7916567 | Twin cell architecture for integrated circuit dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM A twin cell architecture for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM utilizing an open bitline configuration is disclosed. The twin cell architecture disclosed has significant advantages over conventional designs in ... | 03/29/2011 |
| 7902801 | Low dropout regulator with stability compensation circuit The present invention provides a low dropout (LDO) regulator with a stability compensation circuit. A “zero frequency” tracking as well as “non-dominant parasitic poles' frequency reshaping” are performed to achieve a good phase margin for the LDO by means o... | 03/08/2011 |
| 7902764 | Control device for discharge lamp A driving method for a discharge lamp having two cathodes includes providing a supply input voltage for providing an alternating voltage at the terminals of the cathodes, monitoring a condition of each of the cathodes and measuring a first direct voltage signal of t... | 03/08/2011 |
| 7890666 | Embedded protocol selection technique, related interface and computer program product A protocol-based communication between a host device (e.g., MP3 player, digital camera, palmtop, etc.) and an interface (e.g., flash mass storage card) is established automatically by providing protocol-supporting facilities in the interface, each facility supportin... | 02/15/2011 |
| 7890077 | Balanced mixer with calibration of load impedances A calibration device is coupled to a balanced circuit device including first and second outputs provided with first and second load impedances. The calibration device includes an adjusting circuit to adjust the first and second load impedances into a load imbalance ... | 02/15/2011 |
| 7889831 | N-bit shift register controller A column repair circuit uses a system of circuits that automatically stops the shifting of register contents independently of the number of bits to be shifted. The circuit is only dependent on the number of bits in a column address repair block. By adding shift regi... | 02/15/2011 |
| 7889579 | Using differential data strobes in non-differential mode to enhance data capture window A data capture circuit includes strobes that track input data even when conditions arise that cause the differences in skew from interpreting data state ones and zeros. This is accomplished whether these skews arise from reference voltage variation, data pattern loa... | 02/15/2011 |
| 7880508 | Device for detecting the peak value of a signal A device for detecting the peak value of a signal with crest factor not known a priori includes a pair of peak detectors, each of which includes a rectifier element and a discharge-current generator and generates a respective output signal that is a function of the ... | 02/01/2011 |
| 7876137 | Configurable architecture hybrid analog/digital delay locked loop (DLL) and technique with fast open loop digital locking for integrated circuit devices A configurable architecture, hybrid analog/digital delay locked loop and technique with fast open loop digital locking for integrated circuit dynamic random access memory (DRAM) devices and devices incorporating embedded DRAM. The DLL design and technique disclosed ... | 01/25/2011 |
| 7873191 | Capacitive array A capacitive array comprising at least two capacitive entities, comprising a substrate layer. The substrate layer comprises a comb comprising at least four substantially identical teeth, and, for each capacitive entity, a set of fingers comprising one or more interl... | 01/18/2011 |
| RE42035 | Reconfigurable processor module comprising hybrid stacked integrated circuit die elements A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, ... | 01/18/2011 |
| 7812583 | Management of regulator-induced switching noise for sampled systems A system includes a sampler to sample an input voltage and a switching regulator. The switching regulator is adapted to regulate a switching operation of the regulator in response to the sampling by the sampler. ... | 10/12/2010 |
| 7801207 | Signal processing task scheduling in a communication apparatus A communication apparatus includes a radio frequency (RF) circuit configured to operate on an RF signal, and a digital processing circuit that is coupled to the RF circuit. The digital processing circuit may operate in association with the RF circuit according to a ... | 09/21/2010 |
| 7800429 | Temperature insensitive reference circuit for use in a voltage detection circuit A simple voltage detection circuit has few circuit elements, but provides a voltage output that is substantially temperature insensitive. The voltage detection circuit includes a diode-connected transistor, a cascode-connected transistor, as well as first and second... | 09/21/2010 |
| 7782080 | High capacitive load and noise tolerant system and method for controlling the drive strength of output drivers in integrated circuit devices An output driver calibration circuit includes a programmable drive strength output pullup driver including a strongest transistor and a number of other transistors, a programmable drive strength output pulldown driver including a strongest transistor and a number of... | 08/24/2010 |
