Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 6396158 | Semiconductor device and a process for designing a mask Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes ... | 05/28/2002 |
| 6285066 | Semiconductor device having field isolation Narrow and wide, planar field isolation region (72, 74, 152, 172, 182) is formed by forming trenches (52, 54) within a substrate (10). For wide, planar field isolation regions (72, 152, 172, 182), the trenches (52) define at least one mesa (76, 150, 170, ... | 09/04/2001 |
| 6232235 | Method of forming a semiconductor device In one embodiment, a first dielectric film (24), and a second dielectric film (32) are formed over a substrate (10). The substrate is cured to at least partially change a property of the second dielectric film thereby forming an intermediate etch stop (46... | 05/15/2001 |
| 6218733 | Semiconductor device having a titanium-aluminum compound The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas... | 04/17/2001 |
| 6184073 | Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or region A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at lea... | 02/06/2001 |
| 6174425 | Process for depositing a layer of material over a substrate An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current... | 01/16/2001 |
| 6146250 | Process for forming a semiconductor device Vibrating and oscillating rates can be dynamically changed during polishing to achieve an optimal polishing process. A semiconductor device substrate (34) has a first layer with a first film (12) and a second film (10) that overlies the first film (12), w... | 11/14/2000 |
| 6111419 | Method of processing a substrate including measuring for planarity and probing the substrate A substrate (17) is probed after the planarity between a chuck (16) (or the substrate (17)) and a surface of the probing system (20), such as the bottom surface of the interface (28) or test head (22), has been checked. In one method, a measuring tool (30... | 08/29/2000 |
| 6087267 | Process for forming an integrated circuit A process for selectively plasma etching polycrystalline silicon or polysilicon in preference to silicon dioxide which minimizes the detrimental effect of carbon. It has been discovered that carbon from the plasma etch chemicals or from photoresist presen... | 07/11/2000 |
| 6043146 | Process for forming a semiconductor device A buffer film (154, 164) is formed over an underlying film (153, 162) to protect that underlying film (153, 162) from damage during a removal sequence, such as polishing. Scratches, gouging, smearing that can occur to the underlying layer (153, 162) are l... | 03/28/2000 |
| 6012970 | Process for forming a semiconductor device Vibrating and oscillating rates can be dynamically changed during polishing to achieve an optimal polishing process. A semiconductor device substrate (34) has a first layer with a first film (12) and a second film (10) that overlies the first film (12), w... | 01/11/2000 |
| 6008129 | Process for forming a semiconductor device A process for forming via openings (24) between two aluminum-containing interconnects (15) which includes removing a veil material (22) formed during etching of an insulating layer (12), where the veil material (22) is then removed by a combination proces... | 12/28/1999 |
| 5989760 | Method of processing a substrate utilizing specific chuck A substrate (10) having a central region (32) and a peripheral region (34) is processed using a chuck (40) that contacts peripheral regions (34) of the substrate but not the central region. A fabrication step is performed while the substrate (10) is on th... | 11/23/1999 |
| 5985736 | Process for forming field isolation Field isolation regions are formed using oxidation-resistant spacers or plugs that completely fill trenches within a semiconductor substrate prior to forming the field isolation regions. The spacers or plugs help to reduce encroachment of the field isolat... | 11/16/1999 |
| 5985045 | Process for polishing a semiconductor substrate A chemical-mechanical polisher (10) includes a mixer section (12) that mixes components of a polishing fluid prior to introducing the polishing fluid into a polishing section (13) of the polisher (10). In one embodiment, components from feed lines (113 an... | 11/16/1999 |
| 5981340 | Method of building an EPROM cell without drain disturb and reduced select gate resistance A semiconductor device (70) includes a memory cell having a select transistor (67) and a storage transistor (65) having a relatively uniform tunnel dielectric thickness under both the floating gate (651) of the storage transistor and the select gate (671)... | 11/09/1999 |
| 5966619 | Process for forming a semiconductor device having a conductive member that protects field isolation during etching A semiconductor device (150) is formed having a first conductive member (64) overlying a field isolation region (36) that is typically less than two microns wide. Typically, the field isolation region (36) is relatively thinner compared to wider field iso... | 10/12/1999 |
| 5960306 | Process for forming a semiconductor device A process for dry etching a passivation layer (42) of a semiconductor device is performed such that a low radio frequency (RF) power step is used when an underlying bond pad (22) is initially exposed and a high RF power step is used after the initial expo... | 09/28/1999 |
| 5958508 | Process for forming a semiconductor device A metal-semiconductor layer (26) is formed over an insulating layer (20) such that the metal-semiconductor layer (26) is graded to have varying amounts of the semiconductor and metal throughout the layer. In one embodiment, the metal-semiconductor layer (... | 09/28/1999 |
| 5949125 | Semiconductor device having field isolation with a mesa or mesas Narrow and wide, planar field isolation region (72, 74, 152, 172, 182) is formed by forming trenches (52, 54) within a substrate (10). For wide, planar field isolation regions (72, 152, 172, 182), the trenches (52) define at least one mesa (76, 150, 170, ... | 09/07/1999 |
| 5935871 | Process for forming a semiconductor device A process has been developed for a post-chemical mechanical polishing cleaning/passivting step to remove slurry particles (52) and form a passivating film (64) from a portion of an interconnect material within a conductive layer (42) without attacking the... | 08/10/1999 |
| 5928962 | Process for forming a semiconductor device Physical properties of alumina particles in a chemical-mechanical polishing slurry delivery loop (28) are measured using a titration technique (44). Examples of the physical properties include crystallographic phase, surface charge, and surface charge den... | 07/27/1999 |
| 5916011 | Process for polishing a semiconductor device substrate A polishing pad (34) with a poromeric structure polishes two dissimilar materials (56, 58). By using a relatively softer pad. and conditioning, relatively constant times can be used for polishing the dissimilar materials (56, 58). This makes polishing mor... | 06/29/1999 |
| 5918147 | Process for forming a semiconductor device with an antireflective layer Antireflective layers (54, 86, and 109) have been developed that have discrete portions (541, 542, 861, 862, 863, 1091, and 1092). The discrete portions (541, 542, 861, 862, 863, 1091, and 1092) allow the antireflective layers (54, 86, and 109) to be used... | 06/29/1999 |
| 5904547 | Apparatus for dicing a semiconductor device substrate and a process therefor An integrated apparatus (10) has a dicing station (14) and a rinsing/heated drying station (16). In one embodiment, the rinsing/heated drying station (16) has a heater, such as an infrared lamp (36), or uses a heated gas. The integrating apparatus (10) he... | 05/18/1999 |
| 5893752 | Process for forming a semiconductor device A semiconductor device comprises a substrate (100), first conductive film (22 and 32) over the substrate (100), and a second conductive film (54 and 64) over the first conductive film (22 and 32). The first conductive film includes a refractory metal and ... | 04/13/1999 |
| 5888588 | Process for forming a semiconductor device A semiconductor device (10) includes a gate electrode (61) having a silicon/tungsten nitride/tungsten silicon nitride/tungsten silicide composition. The tungsten nitride film (21) and tungsten suicide film (23) are formed using chemical vapor deposition (... | 03/30/1999 |
| 5867032 | Process for testing a semiconductor device Large diameter probe tips (42) can be used to probe a semiconductor device (60). The probe tips (42) are oriented more perpendicular to the surface of the semiconductor device (60) and are less likely to cause damage to the semiconductor device (60). The ... | 02/02/1999 |
| 5863838 | Method for chemically-mechanically polishing a metal layer A method of manufacturing a semiconductor device includes providing (51) a substrate (19), providing (52) a colloid (17) having particles held in suspension, providing (53) a reagent (18), disposing (54) the substrate (19) in a processing tool (10), combi... | 01/26/1999 |
| 5824579 | Method of forming shared contact structure A shared contact structure (30) is formed to electrically connect three coupling layers (59,60,46) to each other and to an active region (33) in a semiconductor substrate (31). A first coupling layer (59) and a second coupling layer (60) are formed such t... | 10/20/1998 |
| 5821168 | Process for forming a semiconductor device A process for forming a semiconductor device (68) in which an insulating layer (52) is nitrided and then covered by a thin adhesion layer (58) before depositing a composite copper layer (62). This process does not require a separate diffusion barrier as a... | 10/13/1998 |
| 5814868 | Transistor having an offset channel section The present invention includes a transistor having a channel region with a first and second section, wherein the sections have lengths that generally perpendicular to one another. The prevent invention also includes the transistor in an SRAM cell and proc... | 09/29/1998 |
| 5814893 | Semiconductor device having a bond pad Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side ... | 09/29/1998 |
| 5812871 | Data processing system and a method of optimizing an operation of the data processing system A data processing system has operational management registers containing attributes that are used during an application to optimize operation of the data processing system for energy, time, or costs based on the type of operation being performed by the da... | 09/22/1998 |
| 5805862 | Method of forming an integrated circuit A simulation input and a model file are generated. The simulation input file is processed to generate object code, entries, line counts, and comment lines. A simulation program is run that uses the object code, entries, line counts, and input comment line... | 09/08/1998 |
| 5781760 | Methods of simulating an electronic circuit design and forming an integrated circuit During an electronic circuit simulation, an input file is generated that has source code and stimulus sections. Each of the source code and stimulus sections includes linking portions that each link a portion of the source code to a portion of the stimulu... | 07/14/1998 |
| 5773326 | Method of making an SOI integrated circuit with ESD protection An SOI structure (20) includes a semiconductor layer (15) formed on an insulating substrate (12). The semiconductor layer (15) is partitioned into an ESD protection portion (32) and a circuitry portion (34). A portion of the semiconductor layer (15) in th... | 06/30/1998 |
| 5769699 | Polishing pad for chemical-mechanical polishing of a semiconductor substrate The present invention includes a polishing pad to improve polishing uniformity across a semiconductor substrate and a method using the polishing pad. The polishing pad has a first region that is closer to the edge of the polishing pad and a second region ... | 06/23/1998 |
| 5750419 | Process for forming a semiconductor device having a ferroelectric capacitor One or more dielectric layers (32, 52) are formed over a ferroelectric capacitor (24) of a FENVM cell, where that the tension within the dielectric layers (32, 52) overlying the ferroelectric capacitor (24) is kept relatively low. By keeping the tension r... | 05/12/1998 |
| 5744841 | Semiconductor device with ESD protection A semiconductor device with an electrostatic discharge (ESD) protection transistor is devised, wherein the ESD protection transistor has halo regions of an opposite conductivity type from the source and drain regions adjacent thereto. In one embodiment, t... | 04/28/1998 |
