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| Number | Title | Issue Date |
| 8180944 | Guest interrupt manager that records interrupts for guests and delivers interrupts to executing guests In an embodiment, a system comprises a memory system and a guest interrupt manager. The guest interrupt manager is configured to receive an interrupt message corresponding to an interrupt that is targeted at a guest executable on the system. The guest interrupt mana... | 05/15/2012 |
| 8176257 | Cache used both as cache and staging buffer In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically alloca... | 05/08/2012 |
| 8174918 | Passgate for dynamic circuitry A dynamic circuit utilizing a passgate on a bit line is disclosed. In one embodiment, a precharge circuit is coupled to a first bit line, while a discharge circuit is coupled to a second bit line. A passgate transistor is coupled between the first bit line and the s... | 05/08/2012 |
| 8171326 | L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication ... | 05/01/2012 |
| 8171258 | Address generation unit with pseudo sum to accelerate load/store operations In an embodiment, an address generation unit (AGU) is configured to generate a pseudo sum from an index portion of two or more operands. The pseudo sum may equal the index if the carry-in of the actual sum to the least significant bit of the index is a selected valu... | 05/01/2012 |
| 8171240 | Misalignment predictor In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the p... | 05/01/2012 |
| 8170828 | Test method using memory programmed with tests and protocol to communicate between device under test and tester In an embodiment, a test method is implemented to test an integrated circuit that includes at least one processor. The method may include programming a memory to which the integrated circuit is coupled during testing with one or more test programs. The integrated ci... | 05/01/2012 |
| 8169764 | Temperature compensation in integrated circuit In an embodiment, an integrated circuit comprises a plurality of temperature sensors and a power manager coupled thereto. The temperature sensors are physically distributed over an area of the integrated circuit that is occupied by logic circuitry implementing the o... | 05/01/2012 |
| 8169246 | Dynamic-to-static converter latch with glitch suppression A latch circuit. The latch circuit may include an input circuit, a precharge circuit, and a transfer circuit. The precharge circuit may precharge a first node during a first phase of a clock signal. Based on an input signal received at a first logic value, the input... | 05/01/2012 |
| 8169236 | Frequency detection mechanism for a clock generation circuit A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency mul... | 05/01/2012 |
| 8169235 | Receiver to match delay for single ended and differential signals In one embodiment, a receiver circuit is provide that may receive either a differential input or a single-ended input corresponding to an interface. The receiver circuit may include at least two current sources to control a gain of an amplification stage in the rece... | 05/01/2012 |
| 8166437 | Automated pad ring generation for programmable logic device implementation of integrated circuit design In an embodiment, a method to automatically generate a pad ring for a programmable logic device implementation of an integrated circuit is contemplated. The pad ring that will be used in the integrated circuit itself may include pad logic (e.g. to support boundary s... | 04/24/2012 |
| 8166316 | Single interface access to multiple bandwidth and power memory zones In an embodiment, a system comprises a first memory module interface unit (MMIU) configured to couple to a first one or more memory modules, and a second MMIU configured to couple to a second one or more memory modules. The first MMIU is configured to operate the fi... | 04/24/2012 |
| 8166276 | Translate and verify instruction for a processor In an embodiment, a first instruction is defined that comprises at least a first operand from which the execution core is configured to determine a virtual address and a second operand that specifies one or more translation attributes that exist in a page table entr... | 04/24/2012 |
| 8166251 | Data prefetcher that adjusts prefetch stream length based on confidence In an embodiment, a processor includes a data cache and a prefetch unit coupled to the data cache. The prefetch unit is configured to identify a prefetch stream in cache misses from the data cache, and the prefetch unit is configured to issue prefetches predicted by... | 04/24/2012 |
| 8156275 | Power managed lock optimization In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may ... | 04/10/2012 |
| 8140945 | Hard component failure detection and correction In one embodiment, a memory controller comprises a check bit encoder circuit coupled to receive a data block to be written to memory, a check/correct circuit coupled to receive an encoded data block read from the memory, and a hard failure detection circuit coupled ... | 03/20/2012 |
| 8140769 | Data prefetcher In an embodiment, a processor includes a data cache and a prefetch unit coupled to the data cache. The prefetch unit is configured to detect one or more prefetch streams corresponding to load operations that miss the data cache, and includes a memory configured to s... | 03/20/2012 |
| 8134874 | Dynamic leakage control for memory arrays A memory circuit is disclosed that comprises a plurality of memory cells coupled to a virtual voltage rail. The plurality of memory cells may form, for example, a sub-array of an SRAM array. A switching circuit may be coupled between the virtual voltage rail and a v... | 03/13/2012 |
| 8134389 | Programmable frequency divider A clock divider and method of operating the same. In various embodiments, the clock divider may be configured to divide clock frequencies by both even and odd divisors. The divisor may be an integer that is represented by an N-bit value, and the clock divider may be... | 03/13/2012 |
| 8134387 | Self-gating synchronizer A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data received from the source clock domain. Under certain conditions, the fir... | 03/13/2012 |
| 8134356 | Operating an integrated circuit at a minimum supply voltage In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the out... | 03/13/2012 |
| 8131946 | Converting victim writeback to a fill In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block ... | 03/06/2012 |
| 8131889 | Command queue for peripheral component In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral compon... | 03/06/2012 |
| 8130572 | Low power memory array column redundancy mechanism A low power memory array column redundancy mechanism includes a memory unit having a memory array and a multiplexer unit. The memory array includes a plurality of columns, which includes a plurality of data columns and one or more unused columns. The multiplexer uni... | 03/06/2012 |
| 8130009 | Dynamic voltage and frequency management In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the t... | 03/06/2012 |
| 8127153 | Memory power profiling In an embodiment, an apparatus comprises one or more registers and a control unit coupled to the one or more registers. The control unit is configured to monitor a power state in one or more memory modules during execution of an application, and to store data genera... | 02/28/2012 |
| 8127098 | Virtualization of real mode execution In one embodiment, a processor is configured to operate in a first mode in which privilege level protection is disabled and paging is enabled. In another embodiment, a method is contemplated including intercepting a write to a control register by a guest executing i... | 02/28/2012 |
| 8125250 | Frequency detection mechanism for a clock generation circuit A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency mul... | 02/28/2012 |
| 8125211 | Apparatus and method for testing driver writeability strength on an integrated circuit An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the drivers may have a different drive strength and each may drive a voltage on... | 02/28/2012 |
| 8120377 | Integrated circuit having secure access to test modes Methods for enabling a secure test mode, and integrated circuits (IC's) implementing the same are disclosed. An IC may include a secure functional unit that is protected from access from test access circuitry during normal operation. The secure functional unit may b... | 02/21/2012 |
| 8120208 | Impedance-based power supply switch optimization In one embodiment, a power gated circuit block includes power switches that couple at least one of the power supply grids within the block to the global power supply grids of the integrated circuit. The power switches receive an enable that indicates whether or not ... | 02/21/2012 |
| 8117404 | Misalignment predictor In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the p... | 02/14/2012 |
| 8108650 | Translation lookaside buffer (TLB) with reserved areas for specific sources In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the req... | 01/31/2012 |
| 8102728 | Cache optimizations using multiple threshold voltage transistors In one embodiment, a memory circuit includes one or more memory cells that include transistors having a first nominal threshold voltage, and interface circuitry such as word line drivers and bit line control circuitry that includes one or more transistors having a s... | 01/24/2012 |
| 8099557 | Push for sharing instruction In one embodiment, a system comprises a first processor, a main memory system, and a cache hierarchy coupled between the first processor and the main memory system. The cache hierarchy comprises at least a first cache. The first processor is configured to execute a ... | 01/17/2012 |
| 8099541 | Minivisor entry point in virtual machine monitor address space In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specif... | 01/17/2012 |
| 8098534 | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and writ... | 01/17/2012 |
| 8097956 | Flexible packaging for chip-on-chip and package-on-package technologies In one embodiment, a packaging solution for an application integrated circuit (IC) and one or more other ICs is provided. The packaging solution may support both chip-on-chip packaging of the application IC (in flip-chip connection to a package substrate) and other ... | 01/17/2012 |
| 8090836 | TCP connection migration A method is provided for migrating a connection between two computing nodes of a computing center. The method includes establishing the connection between a remote application and a local application on a first computing node, pausing the local application, restorin... | 01/03/2012 |
