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| Number | Title | Issue Date |
| 8185571 | Processor for performing multiply-add operations on packed data A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor p... | 05/22/2012 |
| 8171321 | Method and apparatus for cost and power efficient, scalable operating system independent services A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is appl... | 05/01/2012 |
| 8161269 | Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opco... | 04/17/2012 |
| 8103830 | Disabling cache portions during low voltage operations Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operatin... | 01/24/2012 |
| 8103816 | Technique for communicating interrupts in a computer system A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or ope... | 01/24/2012 |
| 8099581 | Synchronizing a translation lookaside buffer with an extended paging table A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), ... | 01/17/2012 |
| 8060974 | Foot-worn scrubbing apparatus Embodiments of foot-worn scrubbing apparatus are disclosed. One embodiment of the apparatus includes a sole made of a suitable sponge material and having a top surface and a bottom surface. A scrubbing surface of another suitable scrubbing material is adhered to the... | 11/22/2011 |
| 7845043 | Foot-worn scrubbing apparatus Embodiments of foot-worm scrubbing apparatus are disclosed. One embodiment of the apparatus includes a sole made of a suitable material and having a top surface and a bottom surface. A scrubbing surface of another suitable material is adhered to the bottom surface o... | 12/07/2010 |
| 7536107 | Optical offset signal cancellation for optical receiver A laser driver for high speed interconnections may convert a digital signal to a current train of a bias mode to represent logical zero and of a modulation mode to represent logical one. An optical signal thus produced may include an optical offset. An optical recei... | 05/19/2009 |
| 7523152 | Methods for supporting extended precision integer divide macroinstructions in a processor A method for an extended precision integer divide algorithm includes separating an L-bit integer dividend into two equal width integer format portions, a first portion including lower M bits of the integer dividend and a second portion including upper M bits of the ... | 04/21/2009 |
| 7516307 | Processor for computing a packed sum of absolute differences and packed multiply-add A method and apparatus is disclosed that computes multiple absolute differences from packed data and sums each one of the multiple absolute differences together to produce a result. According to one embodiment, a processor includes a decode unit to decode a packed s... | 04/07/2009 |
| 7505497 | Laser driver for high speed short distance links One embodiment of a laser driver for high speed interconnections includes a buffered level shifter to shift the input voltage level to an appropriate level. In some embodiments the buffered level shifter may be tuned to provide a desired level shift with impedance m... | 03/17/2009 |
| 7480686 | Method and apparatus for executing packed shift operations A method and apparatus for performing a shift operation on packed data elements having multiple values. One embodiment includes accessing the shift control signal of a first format from a memory. The shift control signal identifyies a first packed shift operation an... | 01/20/2009 |
| 7464208 | Method and apparatus for shared resource management in a multiprocessing system In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. The ... | 12/09/2008 |
| 7461109 | Method and apparatus for providing packed shift operations in a processor A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instr... | 12/02/2008 |
| 7451169 | Method and apparatus for providing packed shift operations in a processor A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the m... | 11/11/2008 |
| 7430578 | Method and apparatus for performing multiply-add operations on packed byte data A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. ... | 09/30/2008 |
| 7424501 | Nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations Nonlinear filtering and deblocking applications utilizing SIMD (single instruction multiple data) sign and absolute value operations are disclosed. The method of one embodiment includes receiving first data for a first block and second data for a second block. The f... | 09/09/2008 |
| 7395304 | Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmetic A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then... | 07/01/2008 |
| 7392275 | Method and apparatus for performing efficient transformations with horizontal addition and subtraction A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs... | 06/24/2008 |
| 7216252 | Method and apparatus for machine check abort handling in a multiprocessing system In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. A ma... | 05/08/2007 |
| 7216138 | Method and apparatus for floating point operations and format conversion operations A method and apparatus are described for converting a number from a floating point format to an integer format or from an integer format to a floating point format responsive to a control signal of a control signal format. Numbers are stored in the floating p... | 05/08/2007 |
