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Pneumatic Shoe Lacing Apparatus
This invention provides a pneumatic shoe lacing apparatus for the pneumatic lacing of shoe.
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| Number | Title | Issue Date |
| 6587931 | Directory-based cache coherency system supporting multiple instruction processor and input/output caches A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/O) units coupled through a shared main memory. The system includes one or more IP cache memo... | 07/01/2003 |
| 6524109 | System and method for performing skill set assessment using a hierarchical minimum skill set definition An improved skill set assessment system and method is disclosed for allowing a user to assess the user's proficiency at performing a predetermined set of skills related to the user's employment position. A user may complete the skill assessment process by... | 02/25/2003 |
| 6477620 | Cache-level return data by-pass system for a hierarchical memory A data by-pass system for a hierarchical, multi-level, memory is disclosed. The by-pass system provides by-pass interfaces between storage devices located at predetermined levels within the memory hierarchy. The hierarchical memory system of the preferred... | 11/05/2002 |
| 6457067 | System and method for detecting faults in storage device addressing logic An improved fault detection system and method for detecting the occurrence of faults within the addressing logic of a storage device is provided. Data stored to a selected address within a storage device includes a copy of the selected address. During a s... | 09/24/2002 |
| 6457101 | System and method for providing the speculative return of cached data within a hierarchical memory system A hierarchical memory structure includes a directory-based main memory coupled to multiple first storage devices, each to store data signals retrieved from the main memory. Ones of the first storage devices are further respectively coupled to second stora... | 09/24/2002 |
| 6401223 | Programmable system for invalidating pending requests within a data processing system A request invalidation system for invalidating pending requests within a data processing system is disclosed. According to the system of the preferred embodiment, one or more requesting units may make requests to gain access to one or more shared resource... | 06/04/2002 |
| 6327593 | Automated system and method for capturing and managing user knowledge within a search system A system and method is provided for allowing users to interactively modify a search index used in performing concept-based searches. The system includes a repository for storing a network of natural language concepts. The repository further stores associa... | 12/04/2001 |
| 6247064 | Enqueue instruction in a system architecture for improved message passing and process synchronization A system and method for adding a queue entry containing message data to a queue shared by communicating, sequential processes includes an enqueue instruction. The enqueue instruction attaches a queue entry to either the tail or the head of the shared queu... | 06/12/2001 |
| 6167479 | System and method for testing interrupt processing logic within an instruction processor A system and method is provided for selectively injecting interrupts within the instruction stream of a data processing system. The system includes a programmable storage device for storing interrupt injection signals, each of which is associated with a r... | 12/26/2000 |
| 6125196 | Method for identifying suspect items in an out-of-balance transaction A method for detecting the most likely source of an error in a document image processing system which processes sets of related documents. A set of characteristics is selected as being indicative that the document image, or item, is the source of the erro... | 09/26/2000 |
| 6055607 | Interface queue with bypassing capability for main storage unit A method of interfacing multiple requests using a request hold register, a multiplexer and a snapshot register with multiple requests directed into both the request hold register and a multiplexer which prevents forwarding the requests to the snapshot reg... | 04/25/2000 |
| 6029205 | System architecture for improved message passing and process synchronization between concurrently executing processes A system and method for interprocess communication between concurrently executing, cooperating sequential processes in a digital computer system uses a shared memory queue as a mechanism for message passing and process synchronization. Data to be transfer... | 02/22/2000 |
| 5915128 | Serial speed-matching buffer utilizing plurality of registers where each register selectively receives data from transferring units or sequentially transfers data to another register A serial speed-matching buffer for transferring data signals between a selectable one of multiple transferring units to one or more receiving units. The serial speed-matching buffer has a plurality of registers which may each be selectably configured in l... | 06/22/1999 |
| 5911083 | Programmable processor execution rate controller A system and method for controlling the execution rate of an instruction processor on an instruction-by-instruction basis in a data processing system. The user controls the execution rate by specifying "cycle-slip" data for each instruction type in the in... | 06/08/1999 |
| 5875462 | Multi-processor data processing system with multiple second level caches mapable to all of addressable memory A cache architecture for a multiprocessor data processing system. The cache architecture includes multiple first-level caches, two second-level caches, and main storage that is addressable by each of the processors. Each first-level cache is dedicated to ... | 02/23/1999 |
| 5875472 | Address conflict detection system employing address indirection for use in a high-speed multi-processor system An improved conflict detection system for use in maintaining memory coherency in a multiprocessor, shared-cache memory system. The system includes a queue for storing pointers to request addresses that resulted in cache misses. The addresses associated wi... | 02/23/1999 |
| 5872910 | Parity-error injection system for an instruction processor A system and method for selectively injecting parity errors into instructions after the instructions are fetched from a storage device and are resident within the instruction processor in a data processing system. The parity errors are selectively injecte... | 02/16/1999 |
