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Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
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| Number | Title | Issue Date |
| 7279406 | Tailoring channel strain profile by recessed material composition control The present invention facilitates semiconductor fabrication by providing methods of fabrication that tailor applied strain profiles to channel regions of transistor devices. A strain profile is selected for the channel regions (104). Recessed regions are form... | 10/09/2007 |
| 7279397 | Shallow trench isolation method A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions (305, 303) of a semiconductor body (306), and a dopant is selectively p... | 10/09/2007 |
| 7276408 | Reduction of dopant loss in a gate structure A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfac... | 10/02/2007 |
| 7268399 | Enhanced PMOS via transverse stress In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regio... | 09/11/2007 |
| 7268088 | Formation of low leakage thermally assisted radical nitrided dielectrics One or more aspects of the present invention relate to forming a dielectric suitable for use as a gate dielectric in a transistor. The gate dielectric is formed by a nitridation process that adds nitrogen to a semiconductor substrate. ... | 09/11/2007 |
| 7268073 | Post-polish treatment for inhibiting copper corrosion Methods (102) are presented for protecting copper structures (26) from corrosion in the fabrication of semiconductor devices (2), wherein a thin semiconductor or copper-semiconductor alloy corrosion protection layer (30) is formed on an e... | 09/11/2007 |
| 7268045 | N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This ... | 09/11/2007 |
| 7262471 | Drain extended PMOS transistor with increased breakdown voltage A semiconductor device (102) that includes a drain extended PMOS transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the PMOS transistor, a drain (124) of the transistor is formed over a region... | 08/28/2007 |
| 7262468 | Method and system for reducing charge damage in silicon-on-insulator technology According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material havi... | 08/28/2007 |
| 7262409 | Chemical etch solution and technique for imaging a device's shallow junction profile The present invention provides, in one aspect, a method of imaging a microelectronics device 100. The method comprises cleaning, when contaminants are preset, a sample of a microelectronics device 100 to be imaged with a first solution comprising hydro... | 08/28/2007 |
| 7262129 | Minimizing resist poisoning in the manufacture of semiconductor devices The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substr... | 08/28/2007 |
| 7256121 | Contact resistance reduction by new barrier stack process The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top port... | 08/14/2007 |
| 7253086 | Recessed drain extensions in transistor device A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate st... | 08/07/2007 |
| 7253072 | Implant optimization scheme The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405... | 08/07/2007 |
| 7253043 | Short channel semiconductor device fabrication The formation of one or more accumulation mode multi gate transistor devices is disclosed. The devices are formed so that short channel effects are mitigated. In particular, one more types of dopant materials are implanted in a channel region, an extension region an... | 08/07/2007 |
| 7250372 | Method for BARC over-etch time adjust with real-time process feedback A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The critical dimension CDresist of the patterned photoresist is measured and a first wafer with me... | 07/31/2007 |
| 7250349 | Method for forming ferroelectric memory capacitor A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched t... | 07/31/2007 |
| 7250334 | Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of... | 07/31/2007 |
| 7244654 | Drive current improvement from recessed SiGe incorporation close to gate A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially... | 07/17/2007 |
| 7244642 | Method to obtain fully silicided gate electrodes The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255 | 07/17/2007 |
| 7241663 | Maskless multiple sheet polysilicon resistor The present invention facilitates semiconductor fabrication of semiconductor devices having polysilicon resistors. An oxide layer is formed over a semiconductor device (104). A polysilicon layer is formed on the oxide layer (106). The polysilicon layer... | 07/10/2007 |
| 7241141 | Low contact SiC boat for silicon nitride stress reduction A vertical wafer boat for supporting at least one semiconductor wafer, formed by a process includes forming a plurality of angled support grooves into a plurality of support members with a groove-making machine. Each support member extends along a longitudinal axis ... | 07/10/2007 |
| 7238623 | Versatile system for self-aligning deposition equipment The present invention provides a system (100) for aligning a dispensing apparatus (110) utilized within a semiconductor deposition chamber (102). A stationary reference apparatus (106) is disposed along the bottom of the deposition chambe... | 07/03/2007 |
| 7238567 | System and method for integrating low schottky barrier metal source/drain According to one embodiment of the invention, a method for integrating low Schottky barrier metal source/drain includes providing a substrate, forming an epitaxial SiGe layer outwardly from the substrate, forming an epitaxial Si layer outwardly from the SiGe layer, ... | 07/03/2007 |
| 7233035 | Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the seco... | 06/19/2007 |
| 7233015 | System and method for detecting liquid flow from a nozzle in a semiconductor processing device A system for detecting liquid flow from a nozzle in a semiconductor processing device includes a first fiber optic sensor, a second fiber optic sensor, and an amp. The first fiber optic sensor and second fiber optic sensor are located on opposite sides of at least o... | 06/19/2007 |
| 7232744 | Method for implanting dopants within a substrate by tilting the substrate relative to the implant source The present invention provides a method for implanting a dopant in a substrate and a method for manufacturing a semiconductor device. The method for implanting a dopant, among other steps, including tilting a substrate (310) located on or over an implant plat... | 06/19/2007 |
| 7228193 | Methods for detecting structure dependent process defects Semiconductor devices formed on wafers are inspected using a master wafer. A subject wafer of a semiconductor design is provided. The subject wafer has dies wherein semiconductor devices of the semiconductor design are formed and at a stage of fabrication. A current... | 06/05/2007 |
| 7227201 | CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-ch... | 06/05/2007 |
| 7226835 | Versatile system for optimizing current gain in bipolar transistor structures Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406 | 06/05/2007 |
| 7226830 | Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. A first oxide layer is formed in core and I/O regions of a semiconductor device (506). The firs... | 06/05/2007 |
| 7226826 | Semiconductor device having multiple work functions and method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over... | 06/05/2007 |
| 7217626 | Transistor fabrication methods using dual sidewall spacers Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is impla... | 05/15/2007 |
| 7216310 | Design method and system for optimum performance in integrated circuits that use power management The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory tra... | 05/08/2007 |
| 7212607 | X-ray confocal defect detection systems and methods An x-ray confocal defect detection system comprises an x-ray source, a confocal component, and defect detectors and operates on a target portion of a semiconductor device. The x-ray source generates x-ray energy. The semiconductor device includes a plurality of form... | 05/01/2007 |
| 7211516 | Nickel silicide including indium and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nicke... | 05/01/2007 |
| 7211481 | Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in ... | 05/01/2007 |
| 7208409 | Integrated circuit metal silicide method Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer i... | 04/24/2007 |
| 7208398 | Metal-halogen physical vapor deposition for semiconductor device defect reduction The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by physical vapor deposition, halogen atoms (120) and transition metal atoms (130)... | 04/24/2007 |
| 7208386 | Drain extended MOS transistor with improved breakdown robustness A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions ( | 04/24/2007 |
