Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 8185698 | Hardware acceleration of a write-buffering software transactional memory A method and apparatus for accelerating a software transactional memory (STM) system is described herein. Annotation field are associated with lines of a transactional memory. An annotation field associated with a line of the transaction memory is initialized to a f... | 05/22/2012 |
| 8176266 | Transaction based shared data operations in a multiprocessor environment The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invali... | 05/08/2012 |
| 8140773 | Using ephemeral stores for fine-grained conflict detection in a hardware accelerated STM A method and apparatus for fine-grained filtering in a hardware accelerated software transactional memory system is herein described. A data object, which may have any arbitrary size, is associated with a filter word. The filter word is in a first default state when... | 03/20/2012 |
| 8132061 | Repair bits for a low voltage cache A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair modu... | 03/06/2012 |
| 8108614 | Mechanism for effectively caching streaming and non-streaming data patterns A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of ... | 01/31/2012 |
| 8099523 | PCI express enhancements and extensions including transactions having prefetch parameters A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system w... | 01/17/2012 |
| 8095932 | Providing quality of service via thread priority in a hyper-threaded microprocessor A method and apparatus for providing quality of service in a multi-processing element environment based on priority is herein described. Consumption of resources, such as a reservation station and a pipeline, are biased towards a higher priority processing element. ... | 01/10/2012 |
| 8086827 | Mechanism for irrevocable transactions A method and apparatus for designating and handling irrevocable transaction is herein described. In response to detecting an irrevocable event, such as an I/O operation, a user-defined irrevocable designation, and a dynamic failure profile, a transaction is designat... | 12/27/2011 |
| 8078831 | Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data pref... | 12/13/2011 |
| 8078807 | Accelerating software lookups by using buffered or ephemeral stores A method and apparatus for accelerating lookups in an address based table is herein described. When an address and value pair is added to an address based table, the value is privately stored in the address to allow for quick and efficient local access to the value.... | 12/13/2011 |
| 8073981 | PCI express enhancements and extensions A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system w... | 12/06/2011 |
| 8065491 | Efficient non-transactional write barriers for strong atomicity A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting i... | 11/22/2011 |
| 8065488 | Mechanism for effectively caching streaming and non-streaming data patterns A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of ... | 11/22/2011 |
| 8060482 | Efficient and consistent software transactional memory A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In... | 11/15/2011 |
| 8041844 | Autodetection of a PCI express device operating at a wireless RF mitigation frequency A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the ... | 10/18/2011 |
| 7996663 | Saving and restoring architectural state for processor cores A method and apparatus for saving and restoring architectural states utilizing hardware is described. A first portion of an architectural state of a processing element, such as a core, is concurrently saved upon being updated. A remaining portion of the architectura... | 08/09/2011 |
| 7996644 | Fair sharing of a cache in a multi-core/multi-threaded processor by dynamically partitioning of the cache An apparatus and method for fairly accessing a shared cache with multiple resources, such as multiple cores, multiple threads, or both are herein described. A resource within a microprocessor sharing access to a cache is assigned a static portion of the cache and a ... | 08/09/2011 |
| 7991966 | Efficient usage of last level caches in a MCMP system using application level configuration This disclosure presents an architectural mechanism which allows a caching bridge to efficiently store data either inclusively or exclusively based upon information configured by an application. An INC bit is set for each access to a page table that indicates whethe... | 08/02/2011 |
| 7984248 | Transaction based shared data operations in a multiprocessor environment The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invali... | 07/19/2011 |
| 7949794 | PCI express enhancements and extensions A method and apparatus for enhancing /extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system ... | 05/24/2011 |
| 7930566 | PCI express enhancements and extensions A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system w... | 04/19/2011 |
| 7899943 | PCI express enhancements and extensions A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system w... | 03/01/2011 |
| 7882339 | Primitives to enhance thread-level speculation A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or mo... | 02/01/2011 |
| 7865670 | Invalidating translation lookaside buffer entries in a virtual machine (VM) system One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the ... | 01/04/2011 |
| 7844801 | Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data pref... | 11/30/2010 |
| 7830166 | Pulse shift modulation for reducing cross-talk of single ended I/O interconnects A method and apparatus is described herein for pulse shift modulation of output waveforms for reducing crosstalk on interconnects. Based on input pulses/bits, an output waveform is selectively delayed by a shift value to ensure transitions in a first direction occur... | 11/09/2010 |
| 7818558 | Method and apparatus for EFI BIOS time-slicing at OS runtime A method and apparatus is described herein for executing firmware tasks during OS runtime. A thread slices execution time among entries in a control structure, such as process control block (PCB), maintained by an OS kernel. An entry in the control structure include... | 10/19/2010 |
| 7814469 | Speculative multi-threading for instruction prefetch and/or trace pre-build The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main t... | 10/12/2010 |
| 7802057 | Priority aware selective cache allocation A method and apparatus for is herein described providing priority aware and consumption guided dynamic probabilistic allocation for a cache memory. Utilization of a sample size of a cache memory is measured for each priority level of a computer system. Allocation pr... | 09/21/2010 |
| 7748001 | Multi-thread processing system for detecting and handling live-lock conditions by arbitrating livelock priority of logical processors based on a predertermined amount of time Method, apparatus and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at least one embodiment, the thread is one of a plurality of active threads in a multiprocessor system that includ... | 06/29/2010 |
| 7743233 | Sequencer address management Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapp... | 06/22/2010 |
| 7730286 | Software assisted nested hardware transactions A method and apparatus for efficiently executing nested transactions is herein described. Hardware support for execution of transactions is provided. Additionally, through the use of logging previous values immediately before a current nested transaction in a local ... | 06/01/2010 |
| 7725662 | Hardware acceleration for a software transactional memory system A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardw... | 05/25/2010 |
| 7716464 | Method to have fault resilient booting A method and apparatus is described herein for fault resilient booting of a platform. Upon booting the platform, any boot routines marked are skipped. A current boot routine to be executed in a boot sequence is registered in nonvolatile memory. An attempt to execute... | 05/11/2010 |
| 7685376 | Method to support heterogeneous memories A method and apparatus is described herein for supporting heterogeneous local memories. A resource affinity table includes an entry for each local memory mapped into an address space. Each entry associating the corresponding local memory with a logical distance, suc... | 03/23/2010 |
| 7685365 | Transactional memory execution utilizing virtual memory Embodiments of the invention relate to transactional memory execution utilizing virtual memory. A processor includes a local transactional cache and a resource manager. The resource manager responsive to a transactional memory transaction request from a requesting t... | 03/23/2010 |
| 7676603 | Write combining protocol between processors and chipsets Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device withou... | 03/09/2010 |
| 7674390 | Zeolite—sol gel nano-composite low k dielectric A method for forming a sol gel-zeolite composite dielectric material is herein described. Zeolite particles may be dispersed in a sol creating a liquid sol-zeolite colloid. The liquid sol-zeolite colloid may be deposited on an underlying layer. The liquid sol-zeolit... | 03/09/2010 |
| 7657880 | Safe store for speculative helper threads The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is permitted to execute Store instructions. Store blocker logic operates to prevent data associated wi... | 02/02/2010 |
| 7647536 | Repair bits for a low voltage cache A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair modu... | 01/12/2010 |
