Did You Know...
...that Charles Goodyear performed some of his experiments on rubber while in debtor's prison? He was there so often he referred to it as his "hotel". Chronically in debt because of poor business sense and ill health, Goodyear depended on the generosity of friends and family. Even after he unlocked the secret to vulcanizing rubber, he was unable to improve his financial situation. When he died, his estate was $200,000 in debt.
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| Number | Title | Issue Date |
| 8185678 | Method and apparatus for controlling a data bus A method and apparatus for controlling a data bus system is provided. A data bus system may use different hardware to perform transceiver and system control functions. The various embodiments of the invention increase compatibility of a data bus system with differen... | 05/22/2012 |
| 8181149 | Interface for managing multiple implementations of a functional block of a circuit design Approaches for assembling an electronic circuit design. A processor performs operations including instantiating and coupling a plurality of instances of functional blocks in the design, including at least one meta block instance. The plurality of instances of functi... | 05/15/2012 |
| 8180820 | Generation of a remainder from division of a first polynomial by a second polynomial Generating a remainder from a division of a first polynomial by a second polynomial having a variable width. One or more embodiments include a first sub-circuit, a first adder, a second sub-circuit, and a second adder. The first sub-circuit is adapted to generate a ... | 05/15/2012 |
| 8180616 | Component tracing in a network packet processing device Approaches for gathering packet processing information. A directed graph is used to represent the packet processing system. In response to each network packet input to the system, an associated, unique packet identifier is established for the network packet. Each in... | 05/15/2012 |
| 8179159 | Configuration interface to stacked FPGA A method of configuring a stacked integrated circuit (“IC”) having a first IC die with configurable logic and a second IC die electrically coupled to the first IC die through an array of inter-chip contacts includes: providing a frame having frame data and a fra... | 05/15/2012 |
| 8178962 | Semiconductor device package and methods of manufacturing the same A semiconductor device package and methods of manufacturing the same are described. In some examples, a semiconductor device includes an IC die including a ring of die pads around a periphery thereof, lands disposed within the ring of die pads, bond terminals couple... | 05/15/2012 |
| 8176461 | Design-specific performance specification based on a yield for programmable integrated circuits A method for generating a design-specific timing specification includes inputting a first timing specification of a target device corresponding to a first timing yield. The first timing specification contains timing delays of elements located in at least first and s... | 05/08/2012 |
| 8176449 | Inference of hardware components from logic patterns The present invention provides a simplified process for inference using a generic logic pattern corresponding to one or more generic functions provided by the hardware component. A circuit design is mapped into a plurality of interconnected hardware components, and ... | 05/08/2012 |
| 8174112 | Integrated circuit device with low capacitance and high thermal conductivity interface An integrated circuit device includes an integrated circuit formed in a semiconductor die and an integrated circuit package containing the semiconductor die. The integrated circuit package includes a thermal interface material substantially between the semiconductor... | 05/08/2012 |
| 8166445 | Estimating Icc current temperature scaling factor of an integrated circuit An embodiment of the present invention reduces resources needed to estimate the Icc Current Temperature Scaling Factor (ITSF) of a device, and provides a method and apparatus to estimate ITSF from the device speed and performance characteristics which can be measure... | 04/24/2012 |
| 8165845 | Method and apparatus for statistical identification of devices based on parametric data A method and apparatus is provided for the calculation of maverick control limits. The maverick control limit method selects the correct parameter(s) as critical parameters to be utilized by the maverick control limit method. Next, the maverick control limit method ... | 04/24/2012 |
| 8161436 | Method and system for transforming fork-join blocks in a hardware description language (HDL) specification The present invention provides a method, system and article of manufacture for the transformation of parallel blocks into synchronized parallel processes that can be simulated without incurring the overhead of creating extra threads or requiring code modifications i... | 04/17/2012 |
| 8160092 | Transforming a declarative description of a packet processor Methods are provided for transforming a declarative description of a processor of the packets of a communication protocol. A first declarative description of the packet processor is input. The first declarative description includes rules that include actions for man... | 04/17/2012 |
| 8159263 | Programmable integrated circuit with voltage domains A programmable integrated circuit having a plurality of individually controlled voltage domains. Each voltage domain includes logic circuitry powered by a respective power network. The voltage magnitude of each power network is independently selectable. Each of a pl... | 04/17/2012 |
| 8156459 | Detecting differences between high level block diagram models A method of detecting differences between high level block diagram models using text based analysis. Previous methods of determining differences between high level block diagram models derive differences through traversal of the block hierarchy which is complex and ... | 04/10/2012 |
| 8155071 | Cross-layer allocation of spectral resource to spatially multiplexed communication A system detects a communication transmitted from multiple transmitting antennas. The system includes a media access controller and a physical block. Based on a signal to noise ratio (SNR), the allocation circuit of the media access controller assigns a portion of a... | 04/10/2012 |
| 8154989 | Recovering a shared channel within a network from a deadlock state A method of processing data within a controller for a network can include identifying frames within a data stream within the network (1110) and detecting a deadlock state according to a number of consecutive frames comprising at least one set control bit (... | 04/10/2012 |
| 8150638 | Predicting parasitic capacitance in schematic circuit simulations using sub-circuit modeling A computer-implemented method of determining parasitic capacitance for transistors within an integrated circuit can include determining a first set of coefficients for a first expression that calculates parasitic capacitance for a transistor structure according to a... | 04/03/2012 |
| 8146035 | Power estimation of a circuit design Approaches for estimating power consumption of a circuit from a circuit design. According to one embodiment, a representation of the circuit design specifies a plurality of circuit elements for implementing the circuit design. The circuit elements are matched to str... | 03/27/2012 |
| 8146028 | Duplicate design flow for mitigation of soft errors in IC operation An integrated circuit (“IC”) (100) is configured to have two instantiations of a user design (103, 105). Register values from the first instantiation (RA1, RA2, RA3, RA4) are compared (102) to corresponding regist... | 03/27/2012 |
| 8145467 | Method and apparatus for profiling a hardware/software embedded system Method and apparatus for profiling a hardware/software embedded system are described. In one example, a hardware co-simulation interface is generated between a programmable logic device (PLD) configured with the embedded system and a computer based on a plurality of... | 03/27/2012 |
| 8145466 | Clustering of electronic circuit design modules for hardware-based and software-based co-simulation platforms Approaches for preparing simulation models of an electronic circuit are disclosed. The design is partitioned into first and second clusters. The design includes a source module in the first cluster connected to a destination module in the second cluster. The first c... | 03/27/2012 |
| 8144825 | Predicting clock period in a semiconductor device A computer-implemented method of predicting a clock period within an integrated circuit can include determining configuration information for the integrated circuit (1430, 1435, 1445) and determining at least one measure of directional shift for an edge of a ... | 03/27/2012 |
| 8144702 | Generation of a pipeline for processing a type of network packets Generating a pipeline for processing a type of network packets. A specification is input of the processing of the type of network packets. The specification specifies actions for inspecting and modifying one or more of the fields of the type of network packets. Assi... | 03/27/2012 |
| 8143987 | Stacked dual inductor structure The dual inductor structure can include a first inductor including a first plurality of coils. Each coil of the first plurality of coils can be disposed within a different one of a plurality of conductive layers. The coils of the first plurality of coils can be vert... | 03/27/2012 |
| 8143976 | High impedance electrical connection via Vias for differential signals are typically of a lower impedance than the signal lines connected to them. The noise and reflected signals resulting in impedance mismatch may require circuits to be operated at a frequency far lower than desired. One or more embodimen... | 03/27/2012 |
| 8143695 | Contact fuse one time programmable memory A fuse structure for a semiconductor integrated circuit (IC) can include a first node comprising a region of a metal layer of an IC manufacturing process and a second node comprising a region of a conductive layer residing on a layer of the IC manufacturing process ... | 03/27/2012 |
| 8143532 | Barrier layer to prevent conductive anodic filaments A through hole is formed in a circuit board that has fibers dispersed in a polymer matrix. Copper is sputtered within the through hole to form a sufficiently conductive layer for electrolytic plating over the sputtered copper layer. ... | 03/27/2012 |
| 8127262 | Communicating state data between stages of pipelined packet processor Approaches for generating a specification of a pipelined packet processor. A textual specification includes input and output packet formats, each specifying a format for each field in the packet and a plurality of actions for processing one or more fields of an inpu... | 02/28/2012 |
| 8122239 | Method and apparatus for initializing a system configured in a programmable logic device Method and apparatus for initializing a system configured in a programmable logic device (PLD) is described. In some examples, the method includes: initializing memory elements in the system with first data; executing a first iteration of the system to process the f... | 02/21/2012 |
| 8122177 | Direct memory access technique for use with PCIe endpoints An integrated circuit (“IC”) includes a peripheral component interconnect express (“PCIe”) root complex having a central processing unit (“CPU”), a memory controller configured to control a main memory of a PCIe system, and a PCIe port coupled to a PCIe ... | 02/21/2012 |
| 8121240 | Statistical measurement of average edge-jitter placement on a clock signal Phase shift is added between a uttering clock signal and a data bit stream clocked by the clock signal. The phase shift is adjusted until half the data bits are captured (counted) over a measurement period. Adding this amount of phase shift between the clock and dat... | 02/21/2012 |
| 8121150 | Method and apparatus for processing variable-length packets in a buffer memory for transmission Method and apparatus for processing variable-length packets in a buffer memory for transmission are described. In some examples, as each packet of the packets is written to a buffer memory, a length of the packet is obtained from a length field therein. For each pac... | 02/21/2012 |
| 8120430 | Stable VCO operation in absence of clock signal A semiconductor device having a phase-locked loop (“PLL”) (100) drives a VCO (114) of the PLL circuit with a first control voltage (VCTRL) produced by a loop filter (112) when a first clock signal (clk_ref) is present. The VCO pro... | 02/21/2012 |
| 8120382 | Programmable integrated circuit with mirrored interconnect structure A programmable integrated circuit (IC) with mirrored interconnect structure. The IC includes a plurality of arrangements, which are horizontally arranged. Each arrangement includes a first logic column, an interconnect column, and a second logic column. Each interco... | 02/21/2012 |
| 8117580 | Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein Memory devices and data structures including multiple configuration bitstreams for programming integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization of partially defective ICs. A user design is implemented two or more ... | 02/14/2012 |
| 8117497 | Method and apparatus for error upset detection and correction A method and apparatus for the detection and correction of soft errors existing within an integrated circuit (IC). Run-time check stops are utilized in conjunction with processor-based, hardware mechanisms to detect and correct soft errors. At run-time, each check s... | 02/14/2012 |
| 8115304 | Method of implementing a discrete element in an integrated circuit A method of implementing a discrete component in an integrated circuit package is described. The method includes steps of coupling the discrete component to a surface of a substrate of the integrated circuit package, coupling an integrated circuit die to the surface... | 02/14/2012 |
| 8098081 | Optimization of interconnection networks A method is implemented for generating a non-blocking routing network design from a crossbar switch-based network design. The non-blocking routing network design includes connections to logic blocks of a programmable integrated circuit. A programmed processor is use... | 01/17/2012 |
| 8091057 | Synthesis, place, and route responsive to reasons for critical paths not meeting performance objective Methods are provided for implementing a design of an integrated circuit meeting a performance objective. A timing analysis for the design specifies critical timing paths that do not meet the performance objective. Reasons are determined for the critical timing paths... | 01/03/2012 |
