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| Number | Title | Issue Date |
| 5714783 | Field-effect transistor A field-effect transistor possesses improved electrostatic discharge characteristics. The transistor (10), formed in a p-type semiconductor substrate, comprises a gate (16) that forms a channel between two adjacent n-regions (12 and 14). At least one of t... | 02/03/1998 |
| 5691089 | Integrated circuits formed in radiation sensitive material and method of forming same A transistor device 10 is disclosed herein. A doped layer 14 of a radiation sensitive material is formed over a substrate 12. The radiation sensitive material 14 may be polyimide, polybenzimidazole, a polymer, an organic dielectrics, a conductor or a semi... | 11/25/1997 |
| 5677041 | Integrated circuits formed in radiation sensitive material and method of forming same A transistor device 10 is disclosed herein. A doped layer 14 of a radiation sensitive material is formed over a substrate 12. The radiation sensitive material 14 may be polyimide, polybenzimidazole, a polymer, an organic dielectrics, a conductor or a semi... | 10/14/1997 |
| 5646601 | Magnetic apparatus for actuating a reed switch and associated system A magnetic apparatus (10) is provided having a bottom plate (12), a top plate (14), a first magnet guide (16), a second magnet guide (18) and a magnet member (20) which is slidable upon a slide axis (22) through apertures (40) and (54) of first magnet gui... | 07/08/1997 |
| 5646430 | Non-volatile memory cell having lightly-doped source region In one embodiment, a non-volatile memory structure 10 comprises heavily doped source 11 and drain 12 regions formed in the surface of a semiconductor substrate 8 and separated by a channel region. 21. A floating gate 13 is formed over and insulated from t... | 07/08/1997 |
| 5640214 | Printer and display systems with bidirectional light collection structures An optical system for directing light to a spatial light modulator 16 (e.g., a digital micro-mirror device) is disclosed herein. This system can be used with displays, printers or cameras. The system includes a first light generating apparatus 30a for gen... | 06/17/1997 |
| 5635740 | Semiconductor device and method of manufacturing the same A semiconductor storage device is disclosed herein. A semiconductor substrate 1 has a first conductive type. A first groove is provided in this semiconductor substrate 1. A second groove 20, which is deeper than the first groove, is provided so as to be s... | 06/03/1997 |
| 5629981 | Information management and security system A closed loop, (networked) information management and security system which provides a secure, end-to-end fully automated solution for controlling access, transmission, manipulation, and auditability of high value information comprising an RFID transponde... | 05/13/1997 |
| 5625370 | Identification system antenna with impedance transformer The present invention discloses an electromagnetic device which includes a magnetic flux producing apparatus for producing a magnetic flux path loop. The magnetic flux producing apparatus preferably comprises a magnetic core 20 surrounded by electrical wi... | 04/29/1997 |
| 5625366 | Flat flexible antenna Apparatus and method for producing a flexible antenna suitable to be incorporated in a badge or similar object. The antenna comprises electrical windings (28, 38) surrounding a flexible antenna core (26, 36). The antenna core (26, 36) is of a material hav... | 04/29/1997 |
| 5617038 | Method and system for screening reliability of semiconductor circuits A method and system for screening semiconductor circuits is disclosed herein. A circuit 50, such as an SOI circuit, is provided. The circuit includes a plurality of transistors and is coupled to a supply voltage node VDD, a reference node V | 04/01/1997 |
| 5612753 | Full-color projection display system using two light modulators A full color projection system is disclosed herein. The projection system includes a means for generating a first light beam and also a means for generating a second light beam. These means may include either separate light sources 10a and 10b or a single... | 03/18/1997 |
| 5592150 | Air coil and method of making the same In one aspect, the present invention provides an air coil 20. The air coil 20 may be made from a strip of electrically conductive material 22 which has an insulating material overlying it. For example, the conductive material may comprise copper. The stri... | 01/07/1997 |
| 5589697 | Charge pump circuit with capacitors A charge pump (10) uses Schottky diodes (12) coupled to clock signals ($c;1 and $c;2) via respective capacitors (14a-d). Regulation and control circuitry 18 provides a stable voltage output and controls the clock circuitry (16)... | 12/31/1996 |
| 5569949 | Area efficient high voltage MOSFETs with vertical RESURF drift regions A high voltage power transistor cell is developed that provides improved RDSon performance without sacrificing breakdown performance through utilization of trench based transistor technology. A source, drain and trench are formed within a substrate. A gat... | 10/29/1996 |
| 5567550 | Method of making a mask for making integrated circuits A transistor device 10 is disclosed herein. A doped layer 14 of a radiation sensitive material is formed over a substrate 12. The radiation sensitive material 14 may be polyimide, polybenzimidazole, a polymer, an organic dielectrics, a conductor or a semi... | 10/22/1996 |
| 5563582 | Integrated air coil and capacitor and method of making the same In one aspect, the present invention provides an integrated inductor and capacitor 20 which can be used as the inductive portion of a resonant circuit and the energy accumulator for a identification system transponder. In a first embodiment, the integrate... | 10/08/1996 |
| 5563430 | Gate array base cell A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon... | 10/08/1996 |
| 5545290 | Etching method The described embodiments of the present invention provide a trench etching technique having a high level of control over the sidewall profile of the trench and a high degree of selectivity to the etch mask. The described embodiments are for etching silic... | 08/13/1996 |
| 5523241 | Method of making infrared detector with channel stops Channel stops for MIS infrared photodetector devices in Hg1-x Cdx Te by lattice damage (454) between and automatically aligned to MIS gates (408). Also, field plates and guard rings are automatically aligned to MIS gates.... | 06/04/1996 |
| 5521524 | Method and system for screening reliability of semiconductor circuits A method and system for screening semiconductor circuits is disclosed herein. A circuit 50, such as an SOI circuit, is provided. The circuit includes a plurality of transistors and is coupled to a supply voltage node VDD, a reference node V | 05/28/1996 |
| 5515319 | Non-volatile memory cell and level shifter A non-volatile memory cell 10 is disclosed herein. The cell is formed in a first semiconductor region 12 of a first conductivity type. A second semiconductor region 14 of a second conductivity type formed over the first semiconductor region 12. A third se... | 05/07/1996 |
| 5506874 | Phase detector and method A phase detector 10 is disclosed herein. A clock signal CLK (OR I), a marker signal MARK (or Q) and a data signal D are provided. The data signal may comprise a periodic clock signal. Sampler circuitry 50 receives the clock signal CLK, the marker signal M... | 04/09/1996 |
| 5502317 | Silicon controlled rectifier and method for forming the same A semiconductor controlled rectifier is disclosed herein. In a preferred embodiment, a first n-doped region 112 is formed in a p-doped semiconductor layer 126. A first n-well region 122 is formed within the first doped region 112. This well 122 extends th... | 03/26/1996 |
| 5491483 | Single loop transponder system and method An apparatus including an object 10 associated with a contactless, electronic identifier is disclosed herein. In one example, the object 10 is a trash bin. This object 10 is formed from a non-conductive material. A single-loop antenna 14 is disposed adjac... | 02/13/1996 |
| 5486494 | Method and apparatus for affixing spheres to a conductive sheet An improved method of affixing spheres 4 to a conductive foil sheet 28 is described herein. A cell matrix is provided. The cell matrix includes a conductive foil matrix 2 with spheres 4 mounted therein. Each of the spheres 4 has an insulating layer 20 dis... | 01/23/1996 |
| 5482880 | Non-volatile memory cell and fabrication method In one embodiment, a non-volatile memory cell structure 10 comprises heavily doped source 11 and drain 12 regions formed in the surface of a semiconductor substrate 8 and separated by a channel region 21. A floating gate 13 is formed over and insulated fr... | 01/09/1996 |
| 5479040 | Charge pump circuit with field oxide regions A charge pump (10) uses Schottky diodes (12) coupled to clock signals (o1 and o2) via respective capacitors (14a-d). Regulation and control circuitry 18 provides a stable voltage output and controls the clock circuitry (16).... | 12/26/1995 |
| 5479034 | Method of making gate array base cell A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon... | 12/26/1995 |
| 5470778 | Method of manufacturing a semiconductor device A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which af... | 11/28/1995 |
| 5465189 | Low voltage triggering semiconductor controlled rectifiers A new semiconductor controlled rectifier which may be used to provide on-chip protection against ESD stress applied at the input, output, power supply pins or between any arbitrary pair of pins of an integrated circuit is disclosed. The structure which ha... | 11/07/1995 |
| 5465058 | Graphics system including an output buffer circuit with controlled Miller effect capacitance An integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rail thereby introducing a controlled amount of Miller effect capacitance in the source follower output... | 11/07/1995 |
| 5465005 | Polysilicon resistor structure including polysilicon contacts An integrated circuit device including at least one polysilicon resistor 10 is disclosed herein. A polysilicon layer 24 is formed, possibly over a field oxide 12. The polysilicon layer 24 is then doped to achieve a selected sheet resistance. An insulating... | 11/07/1995 |
| 5457695 | Method and system for screening logic circuits A method of testing a circuit having one or more memory cells, such as a random access memory, register or latch, is disclosed herein. A selected pattern (e.g., all "1"s, all "0"s, or alternating "1"s and "0"s) is stored (block 10) in each memory cell of ... | 10/10/1995 |
| 5451536 | Power MOSFET transistor A power MOSFET device formed in a face of a semiconductor layer of a first conductivity type is provided. A first, second and third source region of a second conductivity type are formed in the face of the semiconductor layer within a moat and adjacent to... | 09/19/1995 |
| 5448103 | Temperature independent resistor A resistor circuit (and structure) 10 is disclosed herein. A first resistor 14 has a first temperature coefficient of resistance and is coupled to a second resistor 16 which has a second temperature coefficient of resistance, typically opposite to the fir... | 09/05/1995 |
| 5428255 | Gate array base cell with multiple P-channel transistors A gate array base cell (100) performs logic and memory cell functions and comprises a first P-channel transistor (M1) for performing logic functions and having a first predetermined transconductance area and a second P-channel transistor (M5) for performi... | 06/27/1995 |
| 5422852 | Method and system for screening logic circuits A method of testing a circuit having one or more memory cells, such as a random access memory, register or latch, is disclosed herein. A selected pattern (e.g., all "1"s, all "0"s, or alternating "1"s and "0 38 s) is stored (block 10) in each memory cell ... | 06/06/1995 |
| 5420522 | Method and system for fault testing integrated circuits using a light source An improved ICCQ test method uses illumination of the integrated circuit to generate photo-induced currents and diode effects in order to detect types of circuits faults not otherwise detectable using conventional ICCQ testing method... | 05/30/1995 |
| 5410315 | Group-addressable transponder arrangement A responder unit (12) located in spaced relation with respect to an interrogator unit (10) is described. The responder unit (12) has a responder unit receiver (130) for receiving at least one RF interrogation pulse, a responder unit memory (168) containin... | 04/25/1995 |
