Bizarre Patents
An armor with rollers is provided that enables a user to move in all positions by rolling on a hard and smooth surface while constantly varying his bearing points on the ground.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6116768 | Three input arithmetic logic unit with barrel rotator A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. T... | 09/12/2000 |
| 5961635 | Three input arithmetic logic unit with barrel rotator and mask generator A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored i... | 10/05/1999 |
| 5907510 | Write bias generator for column multiplexed static random access memory This invention is useful in column multiplexed memories, particularly static random access memories (SRAM) used in application specific integrated circuits (ASIC) . These column multiplexed memories include memory cells disposed in rows and columns. For w... | 05/25/1999 |
| 5905680 | Self-timed comparison circuits and systems In one embodiment there is a comparison circuit (28) for selecting data in response to a first binary quantity (ADDRESS) and a second binary quantity (TAG). The comparison circuit includes a match circuit (34) for outputting a match signal (MATCH) in resp... | 05/18/1999 |
| 5903742 | Method and circuit for redefining bits in a control register A microprocessor includes a control register having a predetermined bit which is unconditionally writable to either a first state or a second state. Additional bits of the control register are writable to either the first or second state when the predeter... | 05/11/1999 |
| 5850632 | Memory access controller utilizing cache memory to store configuration information A digital data processing system adapts to plural memories having differing address ranges and requiring differing sets of memory access parameters. A memory configuration cache having a stores a plurality of memory configuration cache entries, each inclu... | 12/15/1998 |
| 5838908 | Device for having processors each having interface for transferring delivery units specifying direction and distance and operable to emulate plurality of field programmable gate arrays A virtual field programmable gate array device (20) includes a plurality of processors (22), each containing a central processing unit (24), memory (34), and a network interface (26). Each processor (22) may be programmed to emulate a multiple number of g... | 11/17/1998 |
| 5835421 | Method and apparatus for reducing failures due to bit line coupling and reducing power consumption in a memory A method and apparatus for reducing failures due to bit line coupling and reducing power consumption in a memory (10). The method comprises precharging a first group of bitlines (22) to a first voltage level. Other bit lines (22) are maintained at a secon... | 11/10/1998 |
| 5834335 | Non-metallurgical connection between an integrated circuit and a circuit board or another integrated circuit A method is disclosed for making a non-metallurgical connection between an integrated circuit (16) and either a circuit board (12) or second integrated circuit. In one embodiment, an electrical connection is formed between terminals (28) of an integrated ... | 11/10/1998 |
| 5831451 | Dynamic logic circuits using transistors having differing threshold voltages In a preferred logic circuit embodiment (10), there is a precharge node (14) coupled to be precharged to a precharge voltage (VDD) during a precharge phase and operable to be discharged during an evaluate phase. The circuit also includes a cond... | 11/03/1998 |
| 5826084 | Microprocessor with circuits, systems, and methods for selectively bypassing external interrupts past the monitor program during virtual program operation A microprocessor (26) may multi-task a plurality of programs, and those programs include a virtual program (38 or 40) operable in a virtual mode and a monitor program (34) operable using protected mode semantics. The microprocessor includes input circuitr... | 10/20/1998 |
| 5822579 | Microprocessor with dynamically controllable microcontroller condition selection A microprocessor (5) having a floating-point unit (31) with internal microcode control therein is disclosed. The microcode control is effected by a microsequencer (47) having a microcode ROM (68) and control circuitry (80) therein. A scheduler circuit (50... | 10/13/1998 |
| 5821778 | Using cascode transistors having low threshold voltages In a preferred logic circuit embodiment (164), there is a signal path and a high threshold voltage transistor (46b) having a first threshold voltage and coupled to the signal path. The logic circuit further includes a precharge node (36) coupled to the si... | 10/13/1998 |
| 5815697 | Circuits, systems, and methods for reducing microprogram memory power for multiway branching A processor embodiment comprises a microprogram memory circuit (12) comprising a number of separately energizable banks (14a, 14b). Each of the number of separately energizable banks is operable to concurrently output at least one microinstruction. The pr... | 09/29/1998 |
| 5815005 | Power reduction circuits and systems for dynamic logic gates In a preferred embodiment there is a logic circuit (230) which includes both a first (231) and second (232) phase dynamic logic circuit, where each such circuit has a one or more dynamic logic stages. Each dynamic logic stage includes a precharge node(231... | 09/29/1998 |
| 5815420 | Microprocessor arithmetic logic unit using multiple number representations A microprocessor (5) having at least one arithmetic logic unit, or ALU, (42) for operating upon operands of multiple number representation types is disclosed. The ALU (42) includes a binary logical unit (52) for performing logical operations upon operands... | 09/29/1998 |
| 5809514 | Microprocessor burst mode data transfer ordering circuitry and method The present invention provides a method for transferring groups of data between a microprocessor cache memory (114) and an external memory (105) across a data bus (Bbus). Each group of data includes as many bits of data as the width of the bus (Bubs) with... | 09/15/1998 |
| 5809288 | Synchronized MIMD multi-processing system and method inhibiting instruction fetch on memory access stall There is disclosed a multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. The individual processors can, ... | 09/15/1998 |
| 5805913 | Arithmetic logic unit with conditional register source selection A data processing apparatus having an arithmetic logic unit (230) with conditional register source selection includes a plurality of data registers (200), a status register (210) storing at least one status bit, an arithmetic logic unit (230) and an instr... | 09/08/1998 |
| 5798281 | Method for stressing oxide in MOS devices during fabrication using first and second opposite potentials A method and apparatus are disclosed for stressing the oxide layer (36) of an MOS integrated circuit during the fabrication process. One aspect of the invention is a method for fabricating an MOS integrated circuit. In accordance with this method, an oxid... | 08/25/1998 |
| 5799180 | Microprocessor circuits, systems, and methods passing intermediate instructions between a short forward conditional branch instruction and target instruction through pipeline, then suppressing results if branch taken Circuits, systems, and methods relating to processor which processes a plurality of sequentially arranged instructions. In the method, one method step (10) receives into a processor pipeline an instruction from the plurality of sequentially arranged instr... | 08/25/1998 |
| 5793351 | Video display processor having indication of sprite in excess of the number of sprite registers A video display processor and video display system which overlays mobile patterns called sprites over a background. For each horizontal line the video display processor reads from an external memory data corresponding to sprites appearing on that line. Th... | 08/11/1998 |
| 5787011 | Low-power design techniques for high-performance CMOS circuits A data processing circuit includes first and second signal paths, wherein the first signal path is a speed critical path. The first signal path includes a first logic gate (FIG. 22) for performing a predetermined logic operation, and the second signal pat... | 07/28/1998 |
| 5777382 | Plastic packaging for a surface mounted integrated circuit In accordance with the invention, integrated circuit dies may be packaged in a plastic package employing an area area array technology such as a conductive ball grid array, column grid array or pin grid array. One aspect of the invention is an integrated ... | 07/07/1998 |
| 5767716 | Noise insensitive high performance energy efficient push pull isolation flip-flop circuits An energy efficient D flip-flop circuit has a master latch, a slave latch and a push-pull circuit. This push-pull circuit includes an inverter having an input connected to the output of the master latch and a transmission gate clocked in a second phase ha... | 06/16/1998 |
| 5768609 | Reduced area of crossbar and method of operation There is disclosed a multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The image processor is structured with several individual processors all having communication links to several memories. A crossbar swi... | 06/16/1998 |
| 5765010 | Timing and control circuit and method for a synchronous vector processor A timing and control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This circuit includes a master controller circuit, a vertical timing generator circuit, a... | 06/09/1998 |
| 5761103 | Left and right justification of single precision mantissa in a double precision rounding unit A double precision rounding unit is employed for both single and double precision rounding. Rounding double precision mantissas employs the double precision rounding unit normally. For rounding single precision mantissas, the single precision mantissa is ... | 06/02/1998 |
| 5761726 | Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memorie... | 06/02/1998 |
| 5758195 | Register to memory data transfers with field extraction and zero/sign extension based upon size and mode data corresponding to employed address register A data processing system including a data-memory storing data words having a first data size, and a data processor having an address generator generating addresses pointing to data of a second data size smaller than the first data size. The data processin... | 05/26/1998 |
| 5745421 | Method and apparatus for self-timed precharge of bit lines in a memory A method and apparatus are disclosed for self-timing the precharge of bit lines (22) in a memory array. A reference column bit line (26) is charged to create a reference column voltage. The bit lines (22) in the memory array (12) are precharged until the ... | 04/28/1998 |
| 5742538 | Long instruction word controlling plural independent processor operations A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of prod... | 04/21/1998 |
| 5740411 | Controllably switched phase locked loop circuits, systems, and methods Circuits, systems, and methods, relating to a controllably switched phase locked loop. The system indudes a phase locked loop circuit (16) having a clock signal input (16c), a clock signal lock input (16a), and a clock adjustment signal input (16b). The s... | 04/14/1998 |
| 5734880 | Hardware branching employing loop control registers loaded according to status of sections of an arithmetic logic unit divided into a plurality of sections Conditional hardware branching employs zero overhead loop logic and writing to a loop count register within a program loop. The zero overhead loop logic includes a program counter (701), loop end registers (711, 712, 713), loop start registers (721, 722, ... | 03/31/1998 |
| 5727225 | Method, apparatus and system forming the sum of data in plural equal sections of a single data word This invention is a technique for summing plural sections of a single data word. The technique uses a repeated process forming larger and larger partial sums. Initially the single data word is rotated one section. The original single data word and the rot... | 03/10/1998 |
| 5724599 | Message passing and blast interrupt from processor The invention involves communication within a multiprocessor system. The multiprocessor system includes a command word bus and a plurality of data processors. Each data processor is connected to the command word bus and includes a command circuit, a decod... | 03/03/1998 |
| 5717697 | Test circuits and methods for integrated circuit having memory and non-memory circuits by accumulating bits of a particular logic state An integrated circuit including a semiconductor chip and chip circuitry including memory circuitry and additional non-memory circuitry all fabricated on the semiconductor chip. The chip circuitry has a defined set of locations having logic states includin... | 02/10/1998 |
| 5712999 | Address generator employing selective merge of two independent addresses An address generator (120) forms a selective merge of two addresses. First (610) and second (620) address units generate respective first and second N bit address. Each unit (610, 620) preferrably includes a set of base address registers (611), a set of i... | 01/27/1998 |
| 5710527 | Complementary voltage to current conversion for voltage controlled oscillator A voltage controlled oscillator has a linear voltage to current characteristic from ground to the supply voltage. This oscillator includes a voltage to current converter which employs two output current paths. The first output current path includes an N-t... | 01/20/1998 |
| 5701507 | Architecture of a chip having multiple processors and multiple memories A method of manufacturing integrated circuits uses an architecture having multiple processors and multiple memories, such that there is at least first and second groups of processors and memories. The first group has at least a first processor and at leas... | 12/23/1997 |
