Famous Patents
The first commercial microwave oven was nearly 6 feet tall and weighed in at 750 pounds.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6687796 | Multi-channel DMA with request scheduling A digital system is provided with a multi-channel DMA controller (400) for transferring data between various resources (401, 402). Each channel includes a source port (460-461), a channel controller (410-412) and a destination port (460, 461). Channel to ... | 02/03/2004 |
| 6687292 | Timing phase acquisition method and device for telecommunications systems A timing phase acquisition method and device for burst modems includes an receiver designed to initialize an equalizer filter by matching clock of the equalizer filter of the receiver with the phase of the received signal.... | 02/03/2004 |
| 6608865 | Coding method for video signal based on the correlation between the edge direction and the distribution of the DCT coefficients The objective of the invention is to make high-efficiency compressed coding for images. In coding of video signals in this application example, the edge is extracted in a frame of the input image in block 10. In block 11, classification is made into block... | 08/19/2003 |
| 6606686 | Unified memory system architecture including cache and directly addressable static random access memory A data processing apparatus includes a central processing unit and a memory configurable as cache memory and directly addressable memory. The memory is selectively configurable as cache memory and directly addressable memory by configuring a selected numb... | 08/12/2003 |
| 6606590 | Emulation system with address comparison unit and data comparison unit ownership arbitration In-circuit-emulation of an integrated circuit including a digital data processor capable of executing program instructions selectively assigns emulation resources to either the emulation function or the application program. Each emulation resource can hav... | 08/12/2003 |
| 6606415 | Feedback control for hybrid compression A closed loop feedback system adaptively controls the compression ratio in a Raster Image Processor. The image content is analyzed in real time, and rasterized bitmap is compressed to a sufficient degree to fit into the available frame buffer. This compre... | 08/12/2003 |
| 6594713 | Hub interface unit and application unit interfaces for expanded direct memory access processor An expanded direct memory access processor has ports which may be divided into two sections. The first is an application specific design referred to as the application unit, or application unit. Between the application unit and the expanded direct memory ... | 07/15/2003 |
| 6594711 | Method and apparatus for operating one or more caches in conjunction with direct memory access controller A data processing apparatus includes a data processor core having integral cache memory and local memory, and external memory interface and a direct memory access unit. The direct memory access unit is connected to a single data interchange port of the da... | 07/15/2003 |
| 6594275 | Fibre channel host bus adapter having multi-frequency clock buffer for reduced power consumption A Fiber Channel host bus adapter has a low power, high speed serial to parallel data converter for converting asynchronous serial data into clock aligned, framed, parallel data utilizing a serial in, parallel out register for receiving asynchronous serial... | 07/15/2003 |
| 6591230 | Coprocessor for synthesizing signals based upon quadratic polynomial sinusoids A coprocessor (15) for synthesizing a signal from the sum of sinusoids preferably includes an electronic system (20) having a host processor (12) that forwards frame boundary parameters to the coprocessor (15). Parameter registers (26) in coprocessor (15)... | 07/08/2003 |
| 6590513 | Data acquisition system using predictive conversion A data acquisition system uses an analog-to-digital converter (ADC) that includes a prediction feedback element. Using the computing power of a digital signal processor, the system predicts the next sample of the target signal based on pre-defined rules a... | 07/08/2003 |
| 6574760 | Testing method and apparatus assuring semiconductor device quality and reliability An automatic test apparatus for assuring quality and reliability of semiconductor integrated circuit devices comprising a computerized tester controller performing virtual timing, formatting, and pattern generation for testing said devices; and a test hea... | 06/03/2003 |
| 6574683 | External direct memory access processor implementation that includes a plurality of priority levels stored in request queue An external direct memory access unit includes an event recognizer storing plural event types in an event register, a priority encoder selecting for service one recognized external event, a parameter memory storing service request parameters corresponding... | 06/03/2003 |
| 6571363 | Single event upset tolerant microprocessor architecture A single-event-upset, fault-tolerant data processor architecture enables error detection and correction according to algorithms given. A hardware intensive solution compares signatures of two passes through a block of instructions. A match of signatures g... | 05/27/2003 |
| 6570608 | System and method for detecting interactions of people and vehicles A video surveillance system that implements object detection and event recognition employing smart monitoring algorithms to analyze a video stream and recognize the interaction of people with cars. The system forms a reference image consisting of the back... | 05/27/2003 |
| 6567906 | Secure computing device including virtual memory table look-aside buffer with non-relocatable page of memory A diagnostic program can check the security of a program. The program is stored at predetermined non-relocatable physical address in memory. The diagnostic program is loaded and checks the program at the predetermined physical address against a standard. ... | 05/20/2003 |
| 6567559 | Hybrid image compression with compression ratio control A block based hybrid compression method with compression ratio control. The input page is classified as SOLID, TEXT, SATURATED TEXT or IMAGE type, and the compression method most appropriate for each class is chosen on a block by block basis. The compress... | 05/20/2003 |
| 6567323 | Memory circuit redundancy control A memory having flexible column redundancy and flexible row redundancy plural column sticks, each column stick comprising a plurality of data lines. Positioned on either side of the memory are redundant column sticks each comprising a plurality of data li... | 05/20/2003 |
| 6567182 | Scan conversion of polygons for printing file in a page description language This invention cures many inefficiencies with known scan conversion methods. This invention employs a edge array rather than a set linked list from an array of pointers equal in number to the number of scan lines. This invention thus eliminates storage of... | 05/20/2003 |
| 6563349 | Multiplexor generating a glitch free output when selecting from multiple clock signals A multiplexor generating a glitch free output. A slower clock signal and sleep clock signal are respectively synchronized with positive and negative edges of the faster clock signal. The sleep signal is further synchronized with a negative edge of the slo... | 05/13/2003 |
| 6560288 | Method and system for variable length decoding Variable length codes in a compressed data stream are identified by determining a leading position of a specified value in the compressed data stream. A length of a leading code in the compressed data stream is then determined based on the leading positio... | 05/06/2003 |
| 6554395 | Print head servo and velocity controller with non-linear compensation A print head motor control system uses a desired function of print head position versus time and a measured print head position to form an error signal. The print head controller forms a motor drive signal from the sum of a first term corresponding to the... | 04/29/2003 |
| 6553502 | Graphics user interface for power optimization diagnostics A method of providing a programmer with a visualization of power usage. The method is especially suitable for integration within a debugging process (FIG. 20). A windows-type display (160, 170, 180, 190) displays sections of computer code (160a, 170a), as... | 04/22/2003 |
| 6552573 | System and method for reducing leakage current in dynamic circuits with low threshold voltage transistors A reduced-leakage current dynamic circuit (10) is disclosed that includes a logic circuit (30), a pre-charge transistor (32), and a standby transistor (40). The logic circuit (30) is coupled to an internal output node (50). The logic circuit (30) includes... | 04/22/2003 |
| 6545549 | Remotely controllable phase locked loop clock circuit This invention is a remotely controllable clock circuit embodied in a single integrated circuit device. The clock circuit includes at least one externally writable clock control register, a reference clock input, a controllable oscillator circuit, a pre-s... | 04/08/2003 |
| 6542621 | Method of dealing with occlusion when tracking multiple objects and people in video sequences This invention employs probabilistic templates, or p-templates, which probabilistically encode the rough position and extent of the tracked object's image. The p-templates track objects in the scene, one p-template per object. They can be used to incorpor... | 04/01/2003 |
| 6539061 | Efficient method for decompressing difference coded signals A data processing system for the compression and decompression of data using Differential Pulse Code Modulation, and optimized for fast execution using a parallel processing DSP such as the Texas Instruments TMS320C8X family. Decompression is speeded up o... | 03/25/2003 |
| 6535984 | Power reduction for multiple-instruction-word processors with proxy NOP instructions A method of optimizing assembly code of a VLIW processor (10) or other processor that uses multiple-instruction words (20), each of which comprise instructions to be executed on different functional units (11d and 11e) of the processor (10). The instructi... | 03/18/2003 |
| 6535958 | Multilevel cache system coherence with memory selectively configured as cache or direct access memory and direct memory access A data processing system having a central processing unit, at least one level one cache, a level two unified cache, a directly addressable memory and a direct memory access unit includes a snoop unit generating snoop accesses to the at least one level one... | 03/18/2003 |
| 6532533 | Input/output system with mask register bit control of memory mapped access to individual input/output pins A processing device (10) provides general-purpose input/output pins (52) for use by software routines as needed. A data input register (54) has bits corresponding to each pin (52) for storing the value of the signal on the pin. A data output register (56)... | 03/11/2003 |
| 6532514 | System and method for handling a power supply interruption in a non-volatile memory A system for handling a power supply interruption in a non-volatile memory (10) is disclosed that includes a status indicator set (20) for each sector (16) of a non-volatile memory array (14). The status indicator set (20) is operable to indicate a status... | 03/11/2003 |
| 6530010 | Multiplexer reconfigurable image processing peripheral having for loop control The proposed hardware architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or ups... | 03/04/2003 |
| 6529633 | Parallel difference coding method for lossless compression and real time decompression A block based hybrid compression method where the input page is classified as SOLID, TEXT, SATURATED TEXT or IMAGE type, and the compression method most appropriate for each class is chosen on a block by block basis. Blocks classified as IMAGE may be comp... | 03/04/2003 |
| 6529238 | Method and apparatus for compensation of point noise in CMOS imagers This invention corrects of white spot noise in an imager. If the brightness value of a pixel is greater than the maximum brightness value of eight surrounding pixels, then the compensated output is this maximum brightness value. If the brightness value of... | 03/04/2003 |
| 6526430 | Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing) The proposed architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) ... | 02/25/2003 |
| 6493818 | Technique for pipelining synchronization to maintain throughput across two asynchronous clock domain boundaries This invention is a data synchronous apparatus for synchronization between a first clock domain to a second clock domain asynchronous with the first clock domain. This invention provides for pipelining of data between the two clock domains. Plural synchro... | 12/10/2002 |
| 6492841 | Integrated NAND and flip-flop circuit A combination NAND and flip-flop circuit includes a pre-NAND scan circuit operable to receive a plurality of input signals and produce first and second output signals for receipt by a NAND gate. The plurality of signals comprises signals indicative of a f... | 12/10/2002 |
| 6487687 | Voltage level shifter with testable cascode devices A voltage level shifter with testable cascode devices is disclosed. According to one embodiment, the level shifter includes multiple cascode devices and switches a first output driver according to the values of a data input and an enable input. Testabilit... | 11/26/2002 |
| 6484237 | Unified multilevel memory system architecture which supports both cache and addressable SRAM A data processing apparatus is embodied in a single integrated circuit. The data processing apparatus includes a central processing unit, at least one level one cache, a level two unified cache and a directly addressable memory. The at least one level one... | 11/19/2002 |
| 6483346 | Failsafe interface circuit with extended drain services Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad connection. The interface circuits employ high voltage tolerant, extended drain devices in circuit... | 11/19/2002 |
