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| Number | Title | Issue Date |
| 7734944 | Mechanism for windaging of a double rate driver A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the wo... | 06/08/2010 |
| 7639144 | System and method of validating asset tracking codes A system and method for validating adherence of an UII identifier code to one of several prescribed DOD codes by means of a programmed series of tests. First the code is tested for a prescribed header and a last character message. If one or the other is not found, t... | 12/29/2009 |
| 7478297 | Merged MISR and output register without performance impact for circuits under test The output register of an array and the Multiple Input Signature Register (MISR) logic is implemented with one set of L1/L2 master/slave latches and single additional slave latch. This new combined logic uses less critical area on a chip without a performance impact... | 01/13/2009 |
| 7469399 | Semi-flattened pin optimization process for hierarchical physical designs In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, ... | 12/23/2008 |
| 7170774 | Global bit line restore timing scheme and circuit A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activ... | 01/30/2007 |
| 4791390 | MSE variable step adaptive filter A very rapidly converging adaptive filter which uses a variable scale factor for each weight of the filter. The value of the variable scale factor is chosen for each iteration and is based upon the sign changes of the incremental weight change. The variab... | 12/13/1988 |
| 4791559 | High-speed instruction control for vector processors with remapping An instruction flow control system includes an instruction buffer for receiving stored program instructions. A program address generator signals the instruction buffer for fetching the instructions. A translate RAM decodes the fetched instructions and a t... | 12/13/1988 |
| 4791632 | Compensated laser diode transmitter A compensated laser diode transmitter for high speed data transmission is provided with a pair of current switches, a novel current summing circuit and a novel current sink. The power output of the laser is sensed in real data time and employed to generat... | 12/13/1988 |
| 4788695 | System for decoding self-clocking data signals A coherent detection and decoding circuit coherently recovers data embedded in a self-clocking data signal by recovering the clock in one integrate and dump circuit and recovering the data in a second integrate and dump circuit. The two integrate and dump... | 11/29/1988 |
| 4786392 | Fixture for cleaning a plasma etcher A fixture is provided which cleans a plasma etcher of a type that has a holding member with a surface which holds wafers that are to be etched, and an enclosing member which encloses the holding member to form a chamber for the plasma. This fixture operat... | 11/22/1988 |
| 4776012 | Method of jumping composite PN codes The present invention is concerned with an apparatus and a method of jumping a composite PN code from a current phase position to a desired predetermined phase position so as to enhance acquisition of a composite PN code. The apparatus includes a pluralit... | 10/04/1988 |
| 4772890 | Multi-band planar antenna array A planar array of radiating elements which includes a plurality of radiating elements which are capable of operating upon electromagnetic signals of different frequency bands in a single planar array.... | 09/20/1988 |
| 4763021 | CMOS input buffer receiver circuit with ultra stable switchpoint A CMOS buffer receiver is provided for converting TTL or CMOS input voltage signals to CMOS signals so as to drive CMOS loads on VSLI chips. The buffer receiver comprises a reference voltage generator coupled to a compensation network having an output sig... | 08/09/1988 |
| 4763327 | Distributed digital signal process multiplexer An ultra high frequency multiplexer for combining very high frequency data inputs to produce multiplexed data outputs in the Gigahertz range is provided. Typical ECL output data pulses from integrated circuits are employed as inputs to individual gates of... | 08/09/1988 |
| 4749960 | Long phase-locked carrier recovery loop A long phase-locked loop circuit is provided which has an electronic closure circuit in series in the loop. The loop is effectively an open loop until acquisition of the incoming signal at which time the electronic closure circuit closes the phase-locked ... | 06/07/1988 |
| 4686691 | Multi-purpose register for data and control paths having different path widths A multi-purpose register formed of various cells of a customized integrated circuit gate array chip having input gate cells, multiplexor cells, flip-flop cells and output gate cells. The flip-flop cells may be segmented into registers of different widths ... | 08/11/1987 |
| 4567593 | Apparatus for verification of a signal transfer in a preselected path in a data processing system A specialized circuit set is included in a data processing system wherein the circuit set registers can be configured into a serial array. A clock signal distribution system delivers controlled clock signals to selected serial arrays. A maintenance data p... | 01/28/1986 |
| 4567571 | Memory control for refreshing in a step mode In a computer system, there is included a memory unit which includes a volatile memory store, and a memory control circuit connected with the memory unit thereby permitting the computer system to be operated in a step mode, the memory control circuit comp... | 01/28/1986 |
| 4561053 | Input/output multiplexer for a data processing system In an input/output multiplexer of a data processing unit, a plurality of components, capable of independent activity, provide for the simultaneous execution of a multiplicity of operations involving the exchange of signal groups between a central subsyste... | 12/24/1985 |
| 4556974 | Method for passing a token in a local-area network The method by which the right of access to the common communication medium of an initialized local-area network is transferred between modules having access to the medium by the module having such access transmitting a token to a designated existing and p... | 12/03/1985 |
| 4556939 | Apparatus for providing conflict-free highway access An interface apparatus, which interfaces a communication device to a highway wherein the highway includes a clock line, a data line, and a busy line, comprises a counter element which counts a clock signal transmitted on the clock line to generate a clock... | 12/03/1985 |
| 4553053 | Sense amplifier A sense amplifier for a computer memory includes a plural stage differential amplifier. The first stage of the differential amplifier includes an input emitter follower connected to the input of the first stage differential pair. A negative feedback loop ... | 11/12/1985 |
| 4553201 | Decoupling apparatus for verification of a processor independent from an associated data processing system In a data processing system having a plurality of CPUs, each CPU is operatively connected to other portions of the data processing system through a system interface unit. The CPU includes a cache memory, an execution unit, and a control unit. Further, eac... | 11/12/1985 |
| 4551799 | Verification of real page numbers of stack stored prefetched instructions from instruction cache A cache memory includes a dual or two part cache with one part of the cache being primarily designated for instruction data while the other is primarily designated for operand data, but not exclusively. For a maximum speed of operation, the two parts of t... | 11/05/1985 |
| 4551721 | Method for initializing a token-passing local-area network The method by which a token-passing local-area network having from two to 2n modules is initialized, where n is an integer greater than zero. When connected into the network and energized, each module determines if the network is initialized an... | 11/05/1985 |
| 4542507 | Apparatus for switch path verification The present invention relates to an apparatus for verifying a data path through a digital switch between a transmitting port and a receiving port. The apparatus comprises a transmitter which transmits a test data block in a first predetermined time slot w... | 09/17/1985 |
| 4542420 | Manchester decoder A decoder for Manchester encoded data signals in which the encoded data signals are applied to a first circuit which produces a primary pulse at each voltage transition of the applied signals. The primary pulse enables a delay line oscillator which after ... | 09/17/1985 |
| 4536873 | Data transmission system The present invention relates to a data transmission system wherein a central station having a plurality of router elements exchanges data via a bus which is operatively connected to each router element. Further, each router element is connected to a next... | 08/20/1985 |
| 4530052 | Apparatus and method for a data processing unit sharing a plurality of operating systems Apparatus and method for a supervisor for data processing system capable of utilizing a plurality of operating systems. The supervisor includes apparatus for identifying a condition in the data processing system requiring a different operating system. A r... | 07/16/1985 |
| 4527238 | Cache with independent addressable data and directory arrays Cache memory includes a dual or two part cache with one part of the cache being primarily designated for instruction data while the other is primarily designated for operand data, but not exclusively. For a maximum speed of operation, the two parts of the... | 07/02/1985 |
| 4525714 | Programmable logic array with test capability in the unprogrammed state A programmable circuit array comprises an input buffer adapted to receive a plurality of input signals for outputting equivalent input signals and inverted input signals. A programmable product array receives the equivalent input signals and the inverted ... | 06/25/1985 |
| 4525777 | Split-cycle cache system with SCU controlled cache clearing during cache store access period In a cache memory unit including a cache directory identifying signal groups stored in an associated cache storage unit, apparatus and method are disclosed for searching the cache directory during a second portion of the cache memory cycle when the cache ... | 06/25/1985 |
| 4521692 | Motor generator shutdown circuit for extended ridethrough This invention relates to device for detecting a threshold value of the frequency of an input signal. A gate signal is generated from the input signal, whose period has a relationship to the frequency of the input signal. A counter counts pulses from an o... | 06/04/1985 |
| 4521850 | Instruction buffer associated with a cache memory unit Apparatus and method for providing an improved instruction buffer associated with a cache memory unit. The instruction buffer is utilized to transmit to the control unit of the central processing unit a requested sequence of data groups. In the current in... | 06/04/1985 |
| 4521851 | Central processor A central processor for a general-purpose digital data processing system. The processor has a pair of caches, an operand cache for operands and an instruction cache for instructions, as well as a plurality of execution units, where each execution unit exe... | 06/04/1985 |
| 4514815 | Computerized system and method of material control A system and method for material control to allow tracking and prevent diversion of articles within the system having a computer connected to a visual display, a keyboard, and printer. The computer is also connected to an OCR device for reading labels ass... | 04/30/1985 |
| 4506256 | Annunciator control circuit An annunciator arrangement includes a segmented display unit with segments which may be selectively activated. There is also provided scanning means for scanning a fault line from each of a number of computer components such as voltage regulators to deter... | 03/19/1985 |
| 4506340 | Method and apparatus for producing the residue of the product of two residues Method and apparatus for producing the residue of the product of a multiplier and a multiplicand where the multiplier, multiplicand and product are residues with respect to a check base m, and where m=(2b -1) and b is the number of bits in a re... | 03/19/1985 |
| 4506345 | Data alignment circuit The present invention relates to an alignment network for aligning data words having a plurality of data word formats. A plurality of shifters are utilized, each shifter utilized to shift the corresponding bit of each character. The odd bits, or nonsymmet... | 03/19/1985 |
| 4499579 | Programmable logic array with dynamic test capability in the unprogrammed state The present invention relates to a dynamically testable programmable logic array in an unprogrammed state which adds some circuit components to the static test logic. The static test logic provides the capability to detect stuck-at faults at the input of ... | 02/12/1985 |
