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...that after Walter Hunt patented the safety pin in 1849, he sold the rights to it for $400?
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| Number | Title | Issue Date |
| 5848258 | Memory bank addressing scheme In accordance with the present invention, an apparatus includes a system bus having memory bank identification signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank, and at least one commander module. The... | 12/08/1998 |
| 5809320 | High-performance multi-processor having floating point unit A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queuing between units of the CPU to allow flexibility in in... | 09/15/1998 |
| 5657480 | Method of recording, playback, and re-execution of concurrently running application program operational commands using global time stamps An operator of a digital computer system issues a series of operational commands to respective concurrently executing application programs. Each application program includes a client executive routine that records the application program's operational com... | 08/12/1997 |
| 5657456 | Semiconductor process power supply voltage and temperature compensated integrated system bus driver rise and fall time An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference vol... | 08/12/1997 |
| 5654653 | Reduced system bus receiver setup time by latching unamplified bus voltage An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference vol... | 08/05/1997 |
| 5652869 | System for executing and debugging multiple codes in a multi-architecture environment using jacketing means for jacketing the cross-domain calls A system is provided for executing and debugging multiple codes in a multi-architecture environment that includes a real X architecture (domain) and a simulated (Y) architecture (domain). The multiple code executing and debugging system comprises an X com... | 07/29/1997 |
| 5630097 | Enhanced cache operation with remapping of pages for optimizing data relocation from addresses causing cache misses A computer system executing virtual memory management and having a cache is operated in a manner to reduce cache misses by remapping pages of physical memory from which cache misses are detected. The method includes detecting cache misses, as by observing... | 05/13/1997 |
| 5629840 | High powered die with bus bars Power bus bars are provided for a semiconductor die. Power bus bars are thick electrical conductors that extend the length of the die in an electrically isolated array of stripes. The electrical stripes are divided into two or more interdigitated groups, ... | 05/13/1997 |
| 5627773 | Floating point unit data path alignment A pipelined floating point processor including an add pipe for performing floating point additions described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bi... | 05/06/1997 |
| 5625822 | Using sorting to do matchup in smart recompilation A method and system for compiling a source program using smart recompilation. The invention allows fragments to contain "invocation specific" information, which is generated during a code generation phase of compilation. A hint generator attempts to prese... | 04/29/1997 |
| 5625805 | Clock architecture for synchronous system bus which regulates and adjusts clock skew A synchronous computer system is described. The system is a multiprocessor system having a bus system clock and a processor clock for each processor. The system includes a synchronous computer system bus and a plurality of circuit modules coupled to the s... | 04/29/1997 |
| 5619710 | Method and apparatus for object-oriented invocation of a server application by a client application In response to a message requesting a method invocation from an application or user, a client application determines the proper method to be invoked by retrieving information from a class data base, comparing the retrieved information with user preference... | 04/08/1997 |
| 5619662 | Memory reference tagging A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from th... | 04/08/1997 |
| 5613117 | Optimizing compiler using templates corresponding to portions of an intermediate language graph to determine an order of evaluation and to allocate lifetimes to temporary names for variables A compiler framework uses a generic "shell" and a generic back end (where the code generator is target-specific). The generic back end provides the functions of optimization, register and memory allocation, and code generation. The code generation functio... | 03/18/1997 |
| 5597034 | High performance fan heatsink assembly A fan heatsink assembly is provided to afford cooling for electronic components mounted on a circuit board. The assembly includes a blower mounted on top of a specially shaped heatsink, the heatsink having a truncated hyperbolic shaped central member, wit... | 01/28/1997 |
| 5596754 | Method for performing private lock management Lock management in a distributed data sharing computer system in which resources are shared by servers having local lock managers and the computer system having a global lock manager. Lock modes are defined to govern the availability of resources to the s... | 01/21/1997 |
| 5596218 | Hot carrier-hard gate oxides by nitrogen implantation before gate oxidation A CMOS device is provided having a high concentration of nitrogen atoms at the SiO2 /Si interface reducing hot carrier effects associated with operating shorter devices at voltage levels typically used with longer devices. In one embodiment, th... | 01/21/1997 |
| 5588112 | DMA controller for memory scrubbing A fault tolerant computer system is described in which a direct memory access controller examines the check bit data on every data element that is accessed by the system. The address of any data element that is found to have an error in the check bit data... | 12/24/1996 |
| 5582242 | Thermosiphon for cooling a high power die A thermosiphon provides cooling for a high powered die. The thermosiphon includes a fuse for accommodating temperature fault conditions. The thermosiphon utilizes a water and alcohol mixture for improved boiling characteristics. Contaminants at the joint ... | 12/10/1996 |
| 5568624 | Byte-compare operation for high-performance processor A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations ... | 10/22/1996 |
| 5567651 | Self-aligned cobalt silicide on MOS integrated circuits A method of forming cobalt silicide on source/drain regions and polysilicon gate areas of an MOS integrated circuit uses an improved technique to prevent unwanted oxidation of cobalt or growth of silicide on other areas of device. A thin titanium nitride ... | 10/22/1996 |
| 5565934 | Molded video display screen bezel A method and apparatus for molding a video display screen bezel to a video display device, such as a CRT, is disclosed. The bezel is molded in such a way as to eliminate the need for fasteners between the bezel and the CRT and between the bezel and a hous... | 10/15/1996 |
| 5561328 | Photo-definable template for semiconductor chip alignment A semiconductor chip having a number of bonding pads on one face is mounted on a set of matching, mirror-image bonding pads on a packaging substrate, in a flip chip configuration. An alignment template is formed on and permanently secured to the substrate... | 10/01/1996 |
| 5555382 | Intelligent snoopy bus arbiter The present invention is directed to a method for arbitrating for control of a bus in a multiprocessor system. The multiprocessor system comprises a plurality of processors and a main memory coupled to one another by the bus, each processor including a ca... | 09/10/1996 |
| 5550760 | Simulation of circuits Computational requirements are reduced for executing simulation code for a logic circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the simulation code including data structures associated with ci... | 08/27/1996 |
| 5550729 | Power sequencing control An apparatus for sequencing turn-on and turn-off of power converters includes a first DC to DC converter responsive to a control signal for asserting a voltage supply signal and a sense circuit responsive to the output of said first converter to sense the... | 08/27/1996 |
| 5546354 | Static random access memory having tunable-self-timed control logic circuits A self-timed logic device which produces internal control and timing signals in response to an external signal is described. The circuit includes means responsive to a pulse signal for providing control and timing signals and means responsive to a change ... | 08/13/1996 |
| 5535392 | Using hint generation to cause portions of object files to remain the same A method and system for compiling a source program using smart recompilation. The invention allows fragments to contain "invocation specific" information, which is generated during a code generation phase of compilation. A hint generator attempts to prese... | 07/09/1996 |
| 5526477 | System and method for generating glyphs of unknown characters A method and apparatus for generating glyphs for text elements input to a computer having a memory with at least one look-up table storing glyphs corresponding to such text elements. Each text element is made up of at least one code point, and often of se... | 06/11/1996 |
| 5499364 | System and method for optimizing message flows between agents in distributed computations A distributed computation system has a set of agents that perform each specified distributed computation. State transition events in each agent are conditioned or dependent on state transition events in other ones of the agents participating in the same d... | 03/12/1996 |
| 5481723 | System and method for controlling execution of nested loops in parallel in a computer including multiple processors, and compiler for generating code therefore A system and method for controlling execution of nested loops in parallel in a computer including multiple processors, and a compiler for generating code therefor. The code enables the computer to operate in the following manner. Each processor processes ... | 01/02/1996 |
| 5461351 | Common-mode filtering attachment for power line connectors A filtering attachment is provided for the reduction of common-mode noise in systems. The filtering attachment includes a connector, a ferrite fitted around the connector and a conductive bracket which serves to secure the ferrite around the connector as ... | 10/24/1995 |
| 5461330 | Bus settle time by using previous bus state to condition bus at all receiving locations An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference vol... | 10/24/1995 |
| 5446899 | Hint generation in smart recompilation A method and system for compiling a source program using smart recompilation. The invention allows fragments to contain "invocation specific" information, which is generated during a code generation phase of compilation. A hint generator attempts to prese... | 08/29/1995 |
| 5430888 | Pipeline utilizing an integral cache for transferring data to and from a register A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. ... | 07/04/1995 |
| 5428640 | Switch circuit for setting and signaling a voltage level A switch circuit is disclosed which both sets the voltage at an output terminal and signals that the voltage has been set. The switch circuit may be implemented with a single-pole single-throw switch. A voltage drop device, connected in parallel with the ... | 06/27/1995 |
| 5416907 | Method and apparatus for transferring data processing data transfer sizes A method and apparatus for optimizing the performance of a multibus data processing system is provided. An I/O controller is coupled to the I/O bus and includes MORE bit setting means for initiating a MORE stream transaction on the I/O bus and for thereaf... | 05/16/1995 |
| 5408640 | Phase delay compensator using gating signal generated by a synchronizer for loading and shifting of bit pattern to produce clock phases corresponding to frequency changes A phase delay compensator apparatus is provided which compensates for the phase error caused by propagation delay differences between clock and data paths within a computer system. A look-up table circuit is used to dynamically translate a change in frequ... | 04/18/1995 |
| 5404483 | Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills A processor and method for delaying the processing of cache coherency transactions during outstanding cache fills in a multi-processor system using a shared memory. A first processor fetches data having a specified address by addressing a cache memory, an... | 04/04/1995 |
| 5404482 | Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills A processor and method for preventing access to a locked memory block in a multiprocessor computer system. The processor has a cache memory and records a memory lock in a content-addressable memory separate from the cache memory. Preferably, outstanding c... | 04/04/1995 |
