Did You Know...
...In 1790, the cost to obtain a patent was between $4 and $5.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6184726 | Adjustable level shifter circuits for analog or multilevel memories Level shifter circuits are used to configure analog or multilevel memory cells. A level shifter circuit generates an output voltage that is above the input voltage by an offset voltage value. The magnitude of this offset voltage or the relationship betwee... | 02/06/2001 |
| 6185119 | Analog memory IC with fully differential signal path An integrated circuit memory is capable of storing analog information without the need for A/D conversion. Samples of a analog signal input are stored in nonvolatile memory cells. The integrated circuit is also capable of storing digital information in di... | 02/06/2001 |
| 6181599 | Method for applying variable row BIAS to reduce program disturb in a flash memory storage array Program disturb in a Flash storage array is reduced by applying a voltage level that depends on the threshold level of a previously programmed cell to the word-line of that cell during programming of subsequent cells on the same bit-line. By applying high... | 01/30/2001 |
| 6169503 | Programmable arrays for data conversions between analog and digital Converters such as digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) use conversion arrays containing non-volatile memory cells to provide references that depend on the threshold voltages of the memory cells. The array contains s... | 01/02/2001 |
| 6166606 | Phase and frequency locked clock generator A phase locked loop is described for generating an output clock signal that is both synchronizing with a synchronizing signal and oscillating at substantially the same frequency as required by the system. The phase locked loop as disclosed compares the ti... | 12/26/2000 |
| 6165846 | Method of eliminating gate leakage in nitrogen annealed oxides The improvement of thin tunnel oxides used in EEPROM and FLASH tecnologies using post-oxidation annealing in nitrogen causes defects in subsequent oxide films. These are manifested by oxide thinning at the bird's beak and result in high gate leakage. As t... | 12/26/2000 |
| 6166938 | Data encoding for content addressable memories Input partitioning logic is coupled to bit-lines of a content addressable memory (CAM) array having four-transistor (4-T) non-volatile Flash CAM cells. Prior to a program or search operation on the 4-T Flash CAM cells, two input data bits and their comple... | 12/26/2000 |
| 6160739 | Non-volatile memories with improved endurance and extended lifetime Non-volatile memory cells in a sector of a memory array are selectively erased only when it is determined that the selected memory cells require erasing. A memory cell is selectively erased by applying two non-zero erase voltages to the cell, where the co... | 12/12/2000 |
| 6157558 | Content addressable memory cell and array architectures having low transistor counts An SRAM-based CAM cell and CAM array architecture reduce transistor count and memory size by replacing pass transistors and search transistors of conventional SRAM-base CAM cells with a pair of transistors having gates coupled to bit lines. The two bit-li... | 12/05/2000 |
| 6156653 | Method of fabricating a MOS device Deposited dielectric layers for a semiconductor device are typically formed in a chemical vapor deposition. Often a hydrogen by-product is formed. Especially in a plasma enhanced chemical vapor deposition process, the hydrogen by-product can form free rad... | 12/05/2000 |
| 6157983 | Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associa... | 12/05/2000 |
| 6154793 | DMA with dynamically assigned channels, flexible block boundary notification and recording, type code checking and updating, commands, and status reporting An improved DMA controller is provided. The improved DMA controller uses a peripheral control bus which has scan codes to indicate the DMA channel, conventional data request/data acknowledge lines, and additional lines indicating a "terminate," "type fetc... | 11/28/2000 |
| 6154157 | Non-linear mapping of threshold voltages for analog/multi-level memory An analog-to-analog converter uses programmable conversion arrays containing non-volatile memory cells to provide references that depend on the threshold voltages of the memory cells, with the type of conversion dependent on the threshold voltages of the ... | 11/28/2000 |
| 6154086 | Low ripple power distribution system An apparatus having a power supply terminal, a capacitor terminal, and a load terminal for distributing power from the power supply terminal to the capacitor terminal. The apparatus has a driver which supplies load current to the load terminal in response... | 11/28/2000 |
| 6151246 | Multi-bit-per-cell flash EEPROM memory with refresh A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordan... | 11/21/2000 |
| 6149316 | Flash EEprom system A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased tog... | 11/21/2000 |
| 6148874 | Filling head mechanism that removes material from a spout of a filled container before completely disengaging from the spout A machine and method for filling bags with liquid through spouts attached to the bags, wherein a piston within a filling head that operates to control flow of the liquid from the filling head is also extended out of the filling head and into the spout, af... | 11/21/2000 |
| 6151248 | Dual floating gate EEPROM cell array with steering gates shared by adjacent cells An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floa... | 11/21/2000 |
| 6145360 | Rivet setting device The present invention relates to a rivet setting device having an electric drive motor, at lease one rivet setting means driven by drive motor, at least one rechargeable battery for supplying power to the drive motor, and a circuit for controlling the pow... | 11/14/2000 |
| 6148363 | Device and method for controlling solid-state memory system A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to repl... | 11/14/2000 |
| 6145046 | Universal memory card interface apparatus A removable memory card interface apparatus enables a removable memory card to communicate with a number of peripheral devices directly without the need for the memory card's host or a host computer. The interface apparatus includes a micro-controller ope... | 11/07/2000 |
| 6141849 | Rivet setting device The present invention relates to a rivet setting device having an electric drive motor, a rivet setting means in a crank drive for driving the rivet setting means by the drive motor, wherein the crank drive assumes a rest position in one of its dead-cente... | 11/07/2000 |
| 6134141 | Dynamic write process for high bandwidth multi-bit-per-cell and analog/multi-level non-volatile memories A write process and circuit for a non-volatile memory such as a multi-bit-per-cell Flash memory has multiple local memory arrays and a global bias circuit that charges row lines in the arrays for programming operations. A programming operation in an array... | 10/17/2000 |
| 6134145 | High data rate write process for non-volatile flash memories A non-volatile semiconductor memory includes: multiple write pipelines, each including a memory array; a timing circuit which sequentially starts programming operations in the pipelines; and a shared charge pump and voltage regulation circuit that drives ... | 10/17/2000 |
| 6110752 | Optical techniques of measuring endpoint during the processing of material layers in an optically hostile environment In a process of selectively removing material from an exposed layer carried by a substrate, a technique for determining endpoint by monitoring the intensity of a radiation beam that is passed through the substrate and any intervening layers to be reflecte... | 08/29/2000 |
| 6103555 | Method of improving the reliability of low-voltage programmable antifuse The reliability of an antifuse can be increased and/or the thickness of the antifuse dielectric can be decreased by the use of a rapid thermal nitridation nitride layer as part of the antifuse dielectric. The RTN nitride layer is denser and has fewer pinh... | 08/15/2000 |
| 6103573 | Processing techniques for making a dual floating gate EEPROM cell array An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floa... | 08/15/2000 |
| 6099161 | Asynchronous analog or digital frequency measurement on digital test equipment A method for use with digital automated test equipment for measuring an asynchronous analog frequency, which analog frequency may be up to at least four times the operational frequency of the digital automated test equipment. From test vectors related to ... | 08/08/2000 |
| 6091633 | Memory array architecture utilizing global bit lines shared by multiple cells As a specific application of a new memory architecture, an array of non-volatile dual floating gate memory cells is arranged on a semiconductor substrate with global bit lines extending in a column direction that are either permanently connected, or conne... | 07/18/2000 |
| 6081447 | Wear leveling techniques for flash EEPROM systems A mass storage system made of flash electrically erasable and programmable read only memory ("EEPROM") cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experien... | 06/27/2000 |
| 6077452 | Optical techniques of measuring endpoint during the processing of material layers in an optically hostile environment In a process of selectively removing material from an exposed layer carried by a substrate, a technique for determining endpoint by monitoring the intensity of a radiation beam that is passed through the substrate and any intervening layers to be reflecte... | 06/20/2000 |
| 6078018 | Sorting apparatus Sorting apparatus has a conveyor belt or equivalent mechanism for moving particles at a speed sufficient to generate a stream of particles in air, which particles can be graded such that selected material can be removed. The grading or sorting is conducte... | 06/20/2000 |
| 6072462 | Technique for generating on-screen display characters using software implementation A method for generating a video character in an on-screen display system. The method uses a HALT signal provided to the microprocessor which allows the microprocessor to finish executing its current instruction, but prohibits the microprocessor from begin... | 06/06/2000 |
| 6071262 | System for infusing intravenous nutrition solutions A containment and intravenous delivery bag device for supplying a patient with mixed chemical component nutrients includes a first pouch and a second pouch that are separated by a tube passageway. A frangible valve is fitted within the tube. When the fran... | 06/06/2000 |
| 6070624 | Service-line valve connector and spout valve A quick-disconnect fluid coupling is provided that includes a spout assembly comprising a spout fitment having a first fluid opening and a spout valve member having a second fluid opening and capable of rotating from a first position to a second position ... | 06/06/2000 |
| 6072878 | Multi-channel surround sound mastering and reproduction techniques that preserve spatial harmonics Techniques of making a recording of or transmitting a sound field from either multiple monaural or directional sound signals that reproduce through multiple discrete loud speakers a sound field with spatial harmonics that substantially exactly match those... | 06/06/2000 |
| 6070622 | High speed aseptic filling machine A filling head apparatus for filling a container in sterile conditions. The filling head comprises a regulating valve displaceable in three positions: open position, closed position, and displacement position. The inner wall of the spout of the container ... | 06/06/2000 |
| 6069039 | Plane decode/virtual sector architecture An EEPROM device having a plurality of flash EEPROM cells organized in right and left half memory planes each having right and left quad memory blocks is described along with corresponding control circuitry including erase circuitry for concurrently erasi... | 05/30/2000 |
| 6064707 | Apparatus and method for data synchronizing and tracking An apparatus and method for synchronizing and tracking an input data stream and for generating a synchronous clock therefrom, comprising means for generating a plurality of clock signals oscillating at substantially the same frequency, but with different ... | 05/16/2000 |
| 6061657 | Techniques for estimating charges of delivering healthcare services that take complicating factors into account The expected charges for treating a patient are estimated by the use of linear regression techniques wherein variables and coefficients of estimate models are built from historic patient data of all episode types (inpatient, office visits, etc.) and which... | 05/09/2000 |
