Did You Know...
...that the x-ray was discovered purely by accident? When German physicist Wilhelm Konrad von Roentgen was experimenting with cathode rays in 1895, he put an activated Crookes tube in a book and went out to lunch. When he returned, he discovered that a key that had also been placed in the book showed up as an image on the developed film!
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| Number | Title | Issue Date |
| 6016403 | State machine design for generating empty and full flags in an asynchronous FIFO A state machine for generating a flag that represents the fullness of a FIFO buffer is disclosed. The present invention generates a set of next state variables that are derived generally from a combination of three previous state variables and three addit... | 01/18/2000 |
| 5963056 | Full and empty flag generator for synchronous FIFOs The present invention provides an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags fr... | 10/05/1999 |
| 5955897 | Signal generation decoder circuit and method The present invention provides a circuit and method for manipulating the least significant bit (LSB) of the read and write count signal to generate a glitch free mutually non-exclusive decoder output. The present invention can be used to generate a logic ... | 09/21/1999 |
| 5952670 | Anti-wafer breakage detection system A circuit configured to generate an error signal that may be used to disable a loading mechanism (such as a loading mechanism in a wafer sorter). The circuit comprises a wafer sense circuit configured to generate a first pulse in response to a wafer passi... | 09/14/1999 |
| 5949799 | Minimum-latency data mover with auto-segmentation and reassembly A data mover which provides guaranteed transfer of data between two locations. The data mover includes a pair of data packet memories for input, a pair of data packet memories for output, and a controller which alternately switches each of the paired data... | 09/07/1999 |
| 5935255 | CPU core to bus speed ratio detection A mechanism for determining a CPU's core-to-bus frequency ratio in a computer system using the CPU itself, rather than an external agent, to sample the external pins on RESET and latch their core/bus frequency ratio information into an internal register. ... | 08/10/1999 |
| 5936973 | Test mode latching scheme A novel synchronous latching scheme is disclosed for use in connection with an EPROM device having a limited number of pins for control signals. A negative edge-triggered d-type master-slave latch having a D-input, and a clock input is provided for genera... | 08/10/1999 |
| 5930176 | Multiple word width memory array clocking scheme A circuit for distributing data from a common input source to a number of individual memory cells in a memory array. A multi-bit counter is used to distribute a timing signal to a number of decoder blocks. Each of the decoder blocks receives both a data i... | 07/27/1999 |
| 5926035 | Method and apparatus to generate mask programmable device The present invention concerns a mask-programmed cell comprising an input, an output and a transistor. The transistor has a first terminal and a second terminal. The cell may be configured in a first of three possible states when (a) the cell input is cou... | 07/20/1999 |
| 5926041 | Phase detector with linear output response A parallel sampling phase detector with linear output response is disclosed. The parallel sampling phase detector is disclosed for use in data recovery. The device includes a voltage controlled oscillator (VCO) that generates ten separate phase signals us... | 07/20/1999 |
| 5917335 | Output voltage controlled impedance output buffer The present invention concerns an output buffer, which overcomes previous disadvantages of driving transmission line loads by providing a variable output impedance in response to the load on the output. The buffer generally comprises a pullup device for p... | 06/29/1999 |
| 5912569 | Methods, circuits and devices for improving crossover performance and/or monotonicity, and applications of the same in a universal serial bus (USB) low speed output driver A circuit comprising a first driver circuit, a second driver circuit and a delay circuit. The first driver circuit may be configured to generate a first output signal and a control signal in response to a first input signal. The delay circuit may be confi... | 06/15/1999 |
| 5910742 | Circuit and method for data recovery A circuit and method for synchronizing a data signal to one of a plurality of clocks. The clock may include (i) a pulse generator configured to generate two pulses separated by a delay, (ii) a clock generator configured to generate the plurality of clocks... | 06/08/1999 |
| 5907255 | Dynamic voltage reference which compensates for process variations A dynamic voltage reference circuit for generating one or more control signals for use in controlling a delay circuit or other circuit that requires compensation for process variations. The control signals are generated without drawing DC current at times... | 05/25/1999 |
| 5907784 | Method of making multi-layer gate structure with different stoichiometry silicide layers A method of forming a multi-layer silicide gate structure for a MOS type semiconductor device that includes the processing steps of first providing a substrate, then depositing a gate oxide layer on the substrate, then depositing a first refractory metal ... | 05/25/1999 |
| 5905389 | Methods, circuits and devices for improving crossover performance and/or monotonicity, and applications of the same in a universal serial bus (USB) low speed output driver A circuit comprising a first driver circuit, a second driver circuit and a delay circuit. The first driver circuit may be configured to generate a first output signal and a control signal in response to a first input signal. The delay circuit may be confi... | 05/18/1999 |
| 5903142 | Low distortion level shifter A circuit for generating an output signal in response to an input signal that propagates over devices operating at various supply voltages. The circuit generally comprises a first device operating in a first voltage, a second device operating in a second ... | 05/11/1999 |
| 5900752 | Circuit and method for deskewing variable supply signal paths A circuit and method for deskewing signals by using cross power supply logic paths to compensate for delays created by power supplies operating at different voltages. A first replica circuit operating at a first supply voltage is placed in series with a f... | 05/04/1999 |
| 5898315 | Output buffer circuit and method having improved access The present invention concerns a circuit and method for improving the data access times across boundary reads between cascaded buffers, such as FIFOs, that are connected to a common data output bus. The circuit allows read accesses within a cascaded buffe... | 04/27/1999 |
| 5896069 | Cross coupled differential oscillator A multi-stage apparatus used as a voltage controlled oscillator. Each stage includes a first complementary differential current switch and a second complementary differential current switch with a second set of complementary differential current switches ... | 04/20/1999 |
| 5895481 | Programmable VESA unified memory architecture (VUMA) row address strobe (RAS) A memory controller is disclosed for use in physically mapping a VESA Unified Memory Architecture (VUMA) device, Row Address Strobe signal RAS# to a selected one of a plurality of memory banks. The RAS# signal from the VUMA device is routed to the memory ... | 04/20/1999 |
| 5896068 | Voltage controlled oscillator (VCO) frequency gain compensation circuit A voltage controlled oscillator (VCO) having a current gain compensation circuit includes a control circuit portion for generating a frequency control signal, and a ring oscillator responsive to the frequency control signal for outputting the VCO output s... | 04/20/1999 |
| 5894241 | Bootstrap augmentation circuit and method An augmentation circuit for use in connection with a self-bootstrap type output buffer having an n-channel pullup transistor is disclosed. The augmentation circuit includes a capacitor formed by a second n-channel transistor, connected as a capacitor, and... | 04/13/1999 |
| 5890513 | Non-wearing washer for fluid valve A non-wearing washer for fluid valve is non-fixedly mounted between washer retainer means disposed at a bottom end of a valve stem and the valve seat. The washer is retained in its operative position by configuring its top end to non-fixedly engage the wa... | 04/06/1999 |
| 5886582 | Enabling clock signals with a phase locked loop (PLL) lock detect circuit A circuit for enabling and disabling generation of an output clock signal is disclosed. The circuit includes a PLL lock detect circuit that generates an active lock control signal when an output reference signal of a phase lock loop (PLL) circuit is phase... | 03/23/1999 |
| 5874838 | High voltage-tolerant low voltage input/output cell An improved I/O cell is disclosed which includes a combined p-channel and n-channel transistor pullup configuration. In particular, such combination is connected in series between the chip operating voltage Vcc, and the I/O cell output pad. The... | 02/23/1999 |
| 5862092 | Read bitline writer for fallthru in fifos A method and apparatus for writing data onto the read bitline when a FIFO buffer memory is nearly empty that includes circuitry detecting when a memory is nearly empty, when the read pointer and the write pointer are on the same line with the read pointer... | 01/19/1999 |
| 5860118 | SRAM write partitioning A circuit and method for generating a global write enable signal for use in an SRAM partitioning scheme. The global write enable signal is generated by taking a combination of the individual write enable signals and presenting them as a global write contr... | 01/12/1999 |
| 5850556 | Interruptible state machine An interruptible state machine includes a state machine and an interrupt processor. The interrupt processor minimizes the required total number of states for the state machine when it must return to its next "normal" state after an input or interrupt that... | 12/15/1998 |
| 5848014 | Semiconductor device such as a static random access memory (SRAM) having a low power mode using a clock disable circuit An internal clock signal disable circuit is disclosed for disabling an internal clock signal used in a synchronous static random access memory (SRAM). The reduced power mode is preferably a sleep mode commanded by assertion of a reduced power command sign... | 12/08/1998 |
| 5844271 | Single layer polycrystalline silicon split-gate EEPROM cell having a buried control gate An electrically-erasable programmable read-only memory (EEPROM) cell includes a split-gate read transistor and a buried N-plate control gate. The split gate transistor includes a drain and source regions formed in a P-type silicon substrate with a channel... | 12/01/1998 |
| 5841687 | Interdigitated memory array A method and apparatus to eliminate the problem of requiring sizing of the row and column decoders according to the pitch of the cells in the memory array is to decouple the decoder cell pitch from the memory cell pitch without causing the chip area to in... | 11/24/1998 |
| 5828617 | Multiple word width memory array clocking scheme for reading words from a memory array The present invention provides a circuit for distributing data from a number of individual memory cells in a memory array to a common output. The present invention uses a multi-bit counter to distribute a timing signal to a number of sense amplifier block... | 10/27/1998 |
| 5828262 | Ultra low power pumped n-channel output buffer with self-bootstrap An ultra-low power pumped n-channel transistor output buffer with self-bootstrapping includes an n-channel pullup transistor as the primary pullup device. A gate-to-source capacitance Cgs of the pullup transistor is used to self-bootstrap the i... | 10/27/1998 |
| 5825600 | Fast turn-on silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection An apparatus for protecting an integrated circuit against damage from electrostatic discharge (ESD) includes an ESD bus that is connected to multiple input pads through a respective diode. The ESD bus--the node to be protected--is coupled to the negative ... | 10/20/1998 |
| 5812465 | Redundancy circuit and method for providing word lines driven by a shift register The present invention disables defective rows in a FIFO or other buffer where the word lines of the FIFO buffer are driven by a shift register scheme. Additional enabled rows may be placed within the normal memory array. The additional enabled rows are su... | 09/22/1998 |
| 5809339 | State machine design for generating half-full and half-empty flags in an asynchronous FIFO A state machine design which can be used to realize extremely short flag generation delays, also realizing the benefit of having an extremely high MTBF. A set of next state variables are generated from a combination of three previous state variables and t... | 09/15/1998 |
| 5805003 | Clock frequency synthesis using delay-locked loop A circuit for synthesizing, from a first signal having a first frequency, a second signal having a second frequency. This synthesis includes using a delay locked loop in combination with a minimal amount of logic circuitry to generate a synthesized output... | 09/08/1998 |
| 5793682 | Circuit and method for disabling a bitline load The present invention concerns a circuit and method for disabling the load transistors from the bitlines of a memory array without requiring a fuse. After a particular column is disabled in a redundant memory array system, a short between the particular b... | 08/11/1998 |
| 5793238 | RC delay with feedback The present invention concerns a delay circuit that provides a fixed amount of delay that is generally independent of process variations. An input resistance is provided that may be presented to a threshold device, such as an inverter, that may then be pr... | 08/11/1998 |
