Did You Know...
...that to encourage use of his new invention, the shopping cart, market owner Sylvan Goldman hired fake shoppers to push the carts around his store in Oklahoma City? Seems his customers were reluctant to give up their hand-carried baskets.
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| Number | Title | Issue Date |
| 7646736 | Video conferencing system A method configured to continuously receive frames from a plurality of video channels and transmit to each of a plurality of participants in a video conference individual frames containing information concerning each of the video channels. The method only transmits ... | 01/12/2010 |
| 7593465 | Method for video coding artifacts concealment A method and circuit for processing a reconstructed picture generated from compressed data is disclosed. The method generally includes the steps of (A) estimating a magnitude of coding artifacts created by a coding process for the compressed data based upon the comp... | 09/22/2009 |
| 7567478 | Leakage optimized memory A method of power optimization in a memory is disclosed. The method generally includes the steps of (A) dividing a plurality of bit cells in a design of the memory into (i) a plurality of first rows storing programmed data and (ii) at least one second row storing on... | 07/28/2009 |
| 7408959 | Method and apparatus for ensuring cell ordering in large capacity switching systems and for synchronizing the arrival time of cells to a switch fabric Where links between a port module and plural switch fabric slices are of various lengths, a cell is transmitted from the port module to a switch fabric slice in response to a grant. The transmission is delayed by an amount based on a link round trip delay (RTD) valu... | 08/05/2008 |
| 7400360 | Device for simultaneous display of video at two resolutions with different fractions of active regions An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a decoded video signal. The second circuit may be configured to generate (i) a first video output signal having a first resolution and (ii) a second video s... | 07/15/2008 |
| 7397401 | Arithmetic decode without renormalization costs An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate context information in response to one or more bins on a binary signal. The second circuit may be configured to generate the binary signal in response to (i... | 07/08/2008 |
| 7379422 | Flow control enhancement A networking/communication chip having a receiving buffer or FIFO whereby it receives data from a data source across a network and transfers the data to a host system. The memory in the host system acts as a logical extension of the receiving buffer in the chip; in ... | 05/27/2008 |
| 7376780 | Protocol converter to access AHB slave devices using the MDIO protocol A method for communicating between a first bus and a second bus is disclosed. The method generally includes the steps of (A) recognizing a read operation code in a read frame (i) received from the first bus and (ii) communicated with a first-bus protocol, (B) initia... | 05/20/2008 |
| 7373009 | Method and apparatus for efficient transmission and decoding of quantization matrices A method for encoding quantization matrices comprising the steps of (A) signaling whether values of a luma quantization matrix are determined by either (i) a first set of custom values or (ii) a set of standardized default values, (B) transmitting the first set of c... | 05/13/2008 |
| 7362804 | Graphical symbols for H.264 bitstream syntax elements An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a decoded video signal and syntax elements in response to an encoded bitstream. The second circuit may be configured to generate one or more overlay images ... | 04/22/2008 |
| 7299446 | Enabling efficient design reuse in platform ASICs A design tool for generating design views of a semiconductor chip is presented. The design tool includes an input module, a generation module, a first synthesis module, a user interface module and an extraction module. The input module may be configured to receive i... | 11/20/2007 |
| 7271676 | Method and/or apparatus for implementing a voltage controlled ring oscillator having a multi-peak detected amplitude control loop An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal oscillating at a first frequency in response to (i) a first control signal, and (ii) a second control signal. The second circuit may be con... | 09/18/2007 |
| 7257080 | Dynamic traffic-based packet analysis for flow control An apparatus comprising a plurality of first counters, a second counter, and a logic circuit. The plurality of first counters may each be configured to increment a first value in response to receiving one of a plurality of incoming data packets on an associated port... | 08/14/2007 |
| 7197735 | Floorplan visualization method using gate count and gate density estimations A method for floorplan visualization comprising the steps of (A) receiving design information for an integrated circuit design comprising one or more subsystems, (B) generating one or more gate count estimates for the one or more subsystems of the integrated circuit... | 03/27/2007 |
| 7190413 | Memory video data storage structure optimized for small 2-D data transfer An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the f... | 03/13/2007 |
| 7190368 | Method and/or apparatus for video data storage An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the f... | 03/13/2007 |
| 7181548 | Command queueing engine The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and de... | 02/20/2007 |
| 7170934 | Method and/or apparatus for motion estimation using a hierarchical search followed by a computation split for different block sizes A method for performing motion estimation comprising the steps of (a) determining one or more first vectors representative of a displacement of a first block of a first image in a second image and (b) determining one or more second vectors representative of a displa... | 01/30/2007 |
| 7170561 | Method and apparatus for video and image deinterlacing and format conversion A method and apparatus for deinterlacing a picture is disclosed. The method generally includes the steps of (A) calculating a plurality of differences among a plurality of current samples from a current field of the picture, the differences being calculated along a ... | 01/30/2007 |
| 7154976 | Frequency controller The invention may relate to a digital frequency adjuster for adjusting a first frequency of a first signal. The digital frequency adjuster may comprise a first digital delay line and a first control circuit. The first digital delay line may comprise a plurality of t... | 12/26/2006 |
| 7154887 | Non-blocking grooming switch A grooming switch comprises plural input ports for receiving multi-time-slot input signals and plural output ports for forwarding multi-time-slot output signals. At least five switching stages alternate between time switching and space switching. The first stage is ... | 12/26/2006 |
| 7152193 | Embedded sequence checking A circuit generally including a control function and a checksum function is disclosed. The control function may be configured to assert (i) a start signal in response to a signal having a predetermined sequence of values matching an entry value and (ii) a stop signa... | 12/19/2006 |
| 7138840 | Single VCO/loop filter to control a wobble and read circuit of a DVD and/or CD recorder An apparatus comprising a clock generation circuit, a detect circuit and a select circuit. The clock generator circuit may be configured to generate an output clock signal in response to a control signal. The detect circuit may be configured to generate a detect sig... | 11/21/2006 |
| 7116743 | Digital phase lock loop Techniques of designing a digital phase lock loop are disclosed. In one embodiment, the digital phase lock loop comprises a synchronization unit producing a producing a plurality of clock signals in accordance with a seed clock signal having a frequency, each of the... | 10/03/2006 |
| 7114041 | AMBA modular memory controller A circuit generally comprising a command buffer and a read buffer is disclosed. The command buffer may be configured to (i) buffer a plurality of read commands received by the circuit, wherein each read command has one of a plurality of port values and one of a plur... | 09/26/2006 |
| 7111199 | Built-in debug feature for complex VLSI chip An apparatus comprising (i) a first circuit configured to generate one or more node signals at one or more internal nodes and (ii) a second circuit configured to present one or more of the node signals and a trigger signal in response to one or more control signals.... | 09/19/2006 |
| 7111118 | High performance raid mapping An apparatus generally having a plurality of disk drives and a controller is disclosed. Each of the disk drives may have a first region and a second region. The first regions may have a performance parameter faster than the second regions. The controller may be conf... | 09/19/2006 |
| 7096748 | Embedded strain gauge in printed circuit boards An apparatus generally having a circuit board and a first strain gauge is disclosed. The circuit board may have a plurality of insulating layers. The first strain gauge may be disposed between two of the insulating layers. ... | 08/29/2006 |
| 7092035 | Block move engine with scaling and/or filtering for video or graphics An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to calculate and present an output signal having a first resolution in response to (i) an input signal having a second resolution and (ii) one or more control signals. ... | 08/15/2006 |
| 7091944 | Display controller Systems and methods are disclosed for controlling a display device having a display scan line rate by storing incoming data in a buffer, the buffer having a usage level measure; comparing the usage level to the display scan line rate; and adjusting a width of a disp... | 08/15/2006 |
| 7088979 | Triple conversion RF tuner with synchronous local oscillators An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an upconverted signal in response to an input signal and a first oscillation signal. The second circuit may be configured to generate a dow... | 08/08/2006 |
| 7088351 | Real time image enhancement with adaptive noise reduction and edge detection Systems and methods for controlling a display device include receiving a source video signal from a video source; storing video pixels in one or more line buffers; enhancing the video signal on the fly using data stored in the line buffers; if image enhancement is n... | 08/08/2006 |
| 7076759 | Methodology for generating a modified view of a circuit layout A method for generating a modified view of a circuit layout. In a first step, the method includes receiving the circuit layout from a design rule clean database. In a second step, the method includes extracting a base wafer layout from the circuit layout according t... | 07/11/2006 |
| 7071704 | Circuit for improved diagnosability of defects in a fuse scan structure An apparatus comprising a first control circuit, a second control circuit, a latch circuit and a flip-flop. The first control circuit may be configured to generate a first control signal in response to (i) an input signal from a fuse and (ii) one or more read signal... | 07/04/2006 |
| 7069363 | On-chip bus A bus that may be used in an integrated circuit chip. The bus generally comprises a master interface, a slave interface, and a control logic. The master interface may be configured to (i) receive an early command signal having a predetermined timing relationship to ... | 06/27/2006 |
| 7062739 | Gate reuse methodology for diffused cell-based IP blocks in platform-based silicon products A method for re-using diffused cell-based IP blocks in a structured application specific integrated circuit comprising the steps of (A) implementing one or more blocks of intellectual property (IP) using a plurality of cell-based building blocks and (B) providing on... | 06/13/2006 |
| 7062695 | Memory implementation for handling integrated circuit fabrication faults The present invention may provide a circuit generally having a plurality of addressable memory cells and an access control circuit. The access control circuit may be configured to intercept an access to a faulty cell of the plurality of addressable memory cells. The... | 06/13/2006 |
| 7062577 | AMBA slave modular bus interfaces A circuit generally comprising a plurality of read input registers, a read output register, a write input register and a plurality of write output registers is generally disclosed. The read input registers may be configured to buffer a first read signal received wit... | 06/13/2006 |
| 7061410 | Method and/or apparatus for transcoding between H.264 CABAC and CAVLC entropy coding modes An apparatus comprising a first circuit, a second circuit and an output circuit. The first circuit may be configured to generate (i) one of a first set of entropy coded input signals or a second set of entropy coded input signals and (ii) a data path signal. The sec... | 06/13/2006 |
| 7054988 | Bus interface for processor The present invention may generally provide a processor circuit comprising a processor, a first bus, a bus pipeline stage, and a second bus. The first bus may be coupled to the processor. The bus pipeline stage may be coupled between the first bus and the second bus... | 05/30/2006 |
