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...Daniel Webster invented a "bull plow" to pull out tree stumps. It didn't catch on because it was huge and required four oxen to pull it!
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| Number | Title | Issue Date |
| 7489609 | Advanced high density data write strategy A method of writing a mark to an optical disc includes receiving data to be written and generating a control signal for a laser pulse having a melt period that transitions to a growth period wherein the melt period is characterized by a melt power and the growth per... | 02/10/2009 |
| 7430202 | System and method of tributary time-space switching A tributary time-space switch and a method of switching are provided having low memory requirements. The switch includes a number of inputs and outputs. Each of the inputs receives an input data stream carrying tributary payloads from an external input link that are... | 09/30/2008 |
| 7394707 | Programmable data strobe enable architecture for DDR memory applications An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may include a plurality of first multiplexers and one or more second multiplexers configured to generate a first intermediate enable signal in response to (i) an input e... | 07/01/2008 |
| 7373622 | Relocatable built-in self test (BIST) elements for relocatable mixed-signal elements An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed ar... | 05/13/2008 |
| 7373629 | Distributed relocatable voltage regulator An apparatus comprising an integrated circuit having (i) a number of regions each pre-diffused and configured to be metal-programmed and (ii) a plurality of pins configured to connect the integrated circuit to a socket. A logic portion may be implemented on the inte... | 05/13/2008 |
| 7334207 | Automatic placement based ESD protection insertion An apparatus comprising a plurality of input cells, two or more local tie up cells, and two or more local tie down cells. The plurality of input cells may be configured to provide (i) one or more gate voltage signals and (ii) one or more supply voltage signals. The ... | 02/19/2008 |
| 7330991 | Method and/or apparatus for paging to a dynamic memory array An apparatus comprising a processor, an interface circuit and a memory. The processor may be configured to operate at a first data rate in response to a first clock signal. The interface circuit may be configured to (i) operate in response to the first clock signal,... | 02/12/2008 |
| 7330911 | Accessing a memory using a plurality of transfers A method of operating a circuit, comprising the steps of (A) buffering a read signal received within a plurality of first transfers to the circuit, (B) transmitting the read signal in a second transfer from the circuit, (C) buffering a first write signal received in... | 02/12/2008 |
| 7331028 | Engineering change order scenario manager A method and apparatus for managing a plurality of change orders for a circuit design is disclosed. The method generally includes the steps of (A) receiving the change orders generated manually by a user, (B) analyzing the circuit design with all of the change order... | 02/12/2008 |
| 7301883 | Advanced high density data write strategy A method of writing a mark to an optical disc includes receiving data to be written and generating a control signal for a laser pulse having a melt period that transitions to a growth period wherein the melt period is characterized by a melt power and the growth per... | 11/27/2007 |
| 7290194 | System for performing automatic test pin assignment for a programmable device A tool for facilitating automatic test pin assignment for a programmable platform device including a process for collecting information related to the programmable platform device, a process for automatically initializing a test pin assignment for the programmable p... | 10/30/2007 |
| 7254761 | Platform ASIC reliability A method for monitoring a fabrication of a circuit is disclosed. The method generally includes a step of (A) fabricating a chip only up to and including a first metal layer such that (i) a core region of the chip may has an array of cells, (ii) each of the cells may... | 08/07/2007 |
| 7254720 | Precise exit logic for removal of security overlay of instruction space A circuit generally comprising a first memory, a processor and a logic block is disclosed. The first memory may store (i) a write instruction to store a non-highest security value of at least three security values in a register and (ii) a jump instruction to a secon... | 08/07/2007 |
| 7246216 | Dynamic partitioning of storage media for mixed applications An apparatus comprising a first partition and a second partition. The first partition has a first file system comprising (i) a plurality of first clusters configured to store data having accesses faster than a first worst case data transfer rate and (ii) a dedicated... | 07/17/2007 |
| 7236525 | Reconfigurable computing based multi-standard video codec A circuit generally comprising a multiport memory, a direct memory access engine and a programmable gate array is disclosed. The direct memory access engine may be configured to transfer a first program to the multiport memory. The programmable gate array may be con... | 06/26/2007 |
| 7233622 | Reduced complexity efficient binarization method and/or circuit for motion vector residuals An apparatus comprising a first processing circuit and a second processing circuit. The first processing circuit may be configured to generate a motion vector residual in response to one or more macroblocks of an input signal. The second processing circuit may be co... | 06/19/2007 |
| 7228440 | Scan and boundary scan disable mechanism on secure device A circuit generally comprising a logic module and a security module is disclosed. The logic module may be configured to set a plurality of values to a plurality of predetermined values respectively while in a scan mode. The security module may be configured to (i) d... | 06/05/2007 |
| 7223235 | System and method for monitoring blood pressure from a person Monitoring airflow from a person is accomplished by using a central server arranged to receive and communicate data together with at least one microprocessor-based subsystem. The subsystem includes a microprocessor, a display and a memory. It presents information to... | 05/29/2007 |
| 7202911 | Method and/or circuit for implementing a zoom in a video signal An apparatus comprising a de-interlacer circuit, a rate converter circuit and a zoom circuit. The de-interlacer circuit may be configured to generate a first progressive signal having a first rate in response to an interlaced signal. The rate converter circuit may b... | 04/10/2007 |
| 7197194 | Video horizontal and vertical variable scaling filter An apparatus for variably scaling video picture signals comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more data signals vertically scaled to a first value in response to (i) the video picture signals and (ii)... | 03/27/2007 |
| 7149178 | Method and format for reading and writing in a multilevel optical data systems A system and method for reading and writing in a multilevel optical data system is disclosed. The system provides control signals for timing acquisition, level calibration, DC control, AGC, equalizer training and data synchronization. The user data is ECC protected ... | 12/12/2006 |
| 7082522 | Method and/or apparatus for implementing enhanced device identification An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to present device information in response to one or more externally generated signals. The second circuit may be configured to store the device informa... | 07/25/2006 |
| 7035908 | Method for multiprocessor communication within a shared memory architecture An apparatus comprising a shared memory and a multiprocessor logic circuit. The shared memory may be configured to store data. The multiprocessor logic circuit may comprise a plurality of processors and a message circuit. The message circuit may be configured to pas... | 04/25/2006 |
| 7020200 | System and method for direct motion vector prediction in bi-predictive video frames and fields The present invention is a low complexity method for reducing the number of motion vectors required for bi-predictive frames or fields in digital video streams. The present invention utilizes the motion vectors located in the corner blocks of a co-located macroblock... | 03/28/2006 |
| 7017093 | Circuit and/or method for automated use of unallocated resources for a trace buffer application An apparatus including a first circuit, a second circuit, and a third circuit. The first circuit may be configured to receive a plurality of input signals and present one of the plurality of input signals as a data signal in response to a control signal. The second ... | 03/21/2006 |
| 7010714 | Prescaler architecture capable of non integer division A prescaler generally comprising a first circuit, a multiplexer, and a second circuit. The first circuit may be configured to present a plurality of control signals in response to a first clock signal having a first frequency. The multiplexer may be configured to mu... | 03/07/2006 |
| 7002890 | High density analog recording using write symbols having distinguishable readout waveforms A method of recording data on a recording medium includes mapping the data to a set of write symbols wherein each write symbol represents more than one bit of the data. The set of write symbols is defined by defining a set of variable write parameters; generating a ... | 02/21/2006 |
| 6999132 | RF/IF digital demodulation of video and audio An apparatus generally comprising a tuner circuit, an analog-to-digital circuit and a converter circuit. The tuner circuit may be configured to generate an intermediate frequency signal having a carrier signal at a first intermediate frequency in response to a first... | 02/14/2006 |
| 6999542 | Data ready indicator between different clock domains An apparatus including a first circuit and a second circuit. The first circuit may be configured to present a first data signal and a first indicator signal in response to a first clock signal and an enable signal. The second circuit may be configured to present a s... | 02/14/2006 |
| 6988251 | Efficient implementation of multiple clock domain accesses to diffused memories in structured ASICs A semiconductor device comprising one or more diffused memories and one or more diffused regions. The one or more diffused regions may be configured to provide one or more ports for the one or more diffused memories. ... | 01/17/2006 |
| 6987543 | System to efficiently transmit two HDTV channels over satellite using turbo coded 8PSK modulation for DSS compliant receivers A channel encoding system and a channel decoding system for use in transmitting multiple high definition television programs in a single satellite channel. The channel encoding system may comprise a frame formatter that may be configured to format a transport stream... | 01/17/2006 |
| 6982939 | Write compensation for data storage and communication systems Methods and systems for write compensation for optimizing the performance of a data storage or communication channel are disclosed. In one embodiment, a method comprises determining channel sensitivity to modifications in write signal parameters, detecting systemati... | 01/03/2006 |
| 6980481 | Address transition detect control circuit for self timed asynchronous memories A memory circuit generally comprising a bit cell, a sense amplifier, and a control circuit. The bit cell may be configured to generate a bit signal. The sense amplifier may be configured to generate a reset signal in response to sensing the bit signal. The control c... | 12/27/2005 |
| 6973561 | Processor pipeline stall based on data register status A method of recovering from loading invalid data into a register within a pipelined processor. The method comprises the steps of (A) setting a register status for the register to an invalid state in response to loading invalid data into the register and (B) stalling... | 12/06/2005 |
| 6968420 | Use of EEPROM for storage of security objects in secure systems A circuit generally comprising a first memory, a second memory and a processor is disclosed. The first memory may store an instruction to read an updated security value of at least three security values. The second memory may store (i) the updated security value and... | 11/22/2005 |
| 6915318 | Interpolator A signal interpolator comprises a fractional interpolator and a numeric controlled oscillator. The numeric controlled oscillator may generate a control signal for controlling the fractional interpolator. The numeric controlled oscillator generally comprises a regist... | 07/05/2005 |
| 6907553 | Method and apparatus for estimation of error in data recovery schemes An on-chip data independent method and apparatus for channel error estimation in a data recovery scheme is based on measuring phase noise statistics. The apparatus (10) receives a data pulse and four quadrature clock signals and has a discriminating device ( | 06/14/2005 |
| 6892258 | Hardware semaphores for a multi-processor system within a shared memory architecture A circuit generally comprising a memory element and a controller. The memory element may define a semaphore allocatable to a resource. The controller may be configured to (i) present a granted status in response to a processor reading a first address while the semap... | 05/10/2005 |
| 6871316 | Delay reduction of hardware implementation of the maximum a posteriori (MAP) method A decoder generally comprising a branch metrics circuit and a state metrics circuit. The branch metrics circuit may be configured to generate a plurality of branch metric signals. The state metrics circuit may be configured to (i) add the branch metric signals to a ... | 03/22/2005 |
| 6774952 | Bandwidth management The invention relates to a method and apparatus for vertically scaling a video picture comprising receiving and storing lines of a video frame of a video picture, reading lines of the frame into linestores, applying the lines to a vertical filter and providing an ou... | 08/10/2004 |
