Bizarre Patents
Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
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| Number | Title | Issue Date |
| 8185572 | Data correction circuit A circuit and method are provided for correcting binary values in a data word having N bit positions where the circuit includes several assemblies, each for a unique data word bit position, where each assembly includes a first logic circuit connected to its unique d... | 05/22/2012 |
| 8183145 | Structure and methods of forming contact structures Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the ... | 05/22/2012 |
| 8173532 | Semiconductor transistors having reduced distances between gate electrode regions A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpen... | 05/08/2012 |
| 8130887 | Method and arrangements for link power reduction Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by ... | 03/06/2012 |
| 8129286 | Reducing effective dielectric constant in semiconductor devices Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator ... | 03/06/2012 |
| 8124534 | Multiple exposure and single etch integration method A process including forming a silicon layer over a semiconductor wafer having features thereon and then selectively ion implanting in the silicon layer to form ion implanted regions. The step of selectively ion implanting is repeated as many times as necessary to ob... | 02/28/2012 |
| 8119472 | Silicon device on Si:C SOI and SiGe and method of manufacture A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second mat... | 02/21/2012 |
| 8113123 | Overhead transport service vehicle and method A overhead transport service vehicle system includes a carriage frame structured and arranged to carry a user. A hoisting mechanism utilizes at least one lifting device for lifting and lowering the carriage frame and at least one moving device for causing movement o... | 02/14/2012 |
| 8111903 | Inline low-damage automated failure analysis A system and method for failure analysis of devices on a semiconductor wafer is disclosed. The present invention comprises the use of an inline focused ion beam milling tool to perform milling and image capturing of cross sections of a desired inspection point. The ... | 02/07/2012 |
| 8107800 | Method and structure to control thermal gradients in semiconductor wafers during rapid thermal processing An article supports a workpiece during thermal processing. At least three elongated support members, e.g., support pins, extend upwardly from an element such as support arms for supporting the workpiece. Each of the support members includes a first portion adjacent ... | 01/31/2012 |
| 8107079 | Multi layer alignment and overlay target and measurement method A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with... | 01/31/2012 |
| 8089133 | Optical assemblies for transmitting and manipulating optical beams Optical cubes and optical cube assemblies for directing optical beams are provided. The optical cubes are optically transparent modules that can be adapted to reflect, transmit, and/or partially reflect and transmit optical beams. The optical cubes may include bi-di... | 01/03/2012 |
| 8054867 | Apparatus for transmitting data and additional information simultaneously within a wire-based communication system An apparatus is provided for transmitting data signals and additional information signals having partially overlapping frequency bands simultaneously within a wire based communication system over the same wired medium using a spread spectrum technique for modulating... | 11/08/2011 |
| 8053862 | Integrated circuit fuse An integrated circuit and a fuse therefore are disclosed. The integrated circuit fuses includes a plurality of terminals coupled by a fuse element, wherein the fuse element is located in a non-last metal layer and/or wherein each terminal is fully-landed on an upper... | 11/08/2011 |
| 8039837 | In-line voltage contrast detection of PFET silicide encroachment A semiconductor test structure includes a PFET transistor, having a source region, a drain region, a gate disposed between the source region and the drain region, a body disposed under the gate, and a body contact. The source region and drain region float, and the b... | 10/18/2011 |
| 8037261 | Closed-loop system for dynamically distributing memory bandwidth A closed-loop system for dynamically distributing memory bandwidth between real-time components and non-real-time components is provided. Specifically, the present invention includes monitors for measuring a performance of each of the real-time components. Based on ... | 10/11/2011 |
| 8022685 | Temperature dependent voltage source compensation A circuit and a method for regulating a voltage supply where the method includes the steps of concurrently measuring temperature, IR drop and frequency response within the circuit, adjusting voltage supplied to the circuit in response to the measured temperature, IR... | 09/20/2011 |
| 8021971 | Structure and method to form a thermally stable silicide in narrow dimension gate stacks An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion define... | 09/20/2011 |
| 8021828 | Photoresist compositions and methods related to near field masks A structure and a photolithography method. The method includes forming a first layer of a first photoresist including a first polymer and a first photosensitive acid generator. A second layer of a second photoresist, including a second polymer having at least one ph... | 09/20/2011 |
| 8017303 | Ultra low post exposure bake photoresist materials Polymers comprising a first methacrylate monomer having a pendent spacer between the polymer backbone and an acid-liable acetal group, a second methacrylate monomer having a pendent group including a fluorinated alkyl group and a third methacrylate monomer having a ... | 09/13/2011 |
| 8012863 | Transistors with gate stacks having metal electrodes A transistor with a gate stack having a metal electrode and a method for forming the same. The method includes providing a structure which includes (a) a substrate, (b) a gate dielectric layer on the substrate, and (c) a gate layer on the gate dielectric layer. The ... | 09/06/2011 |
| 8010225 | Method and system of monitoring manufacturing equipment A method and system is provided for monitoring manufacturing equipment and, more particularly, for monitoring manufacturing equipment in a semiconductor fabrication facility using existing tool elements. The method includes operating a tool working at an operating m... | 08/30/2011 |
| 8005880 | Half width counting leading zero circuit A circuit and method are provided for storing a data word in a latch and determining the number of consecutive equal value bits within the data word. The data word consists of bits stored in unique bit positions and having a least significant bit position and a most... | 08/23/2011 |
| 8001495 | System and method of predicting problematic areas for lithography in a circuit design A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface h... | 08/16/2011 |
| 7992734 | Semiconductor automation buffer storage identification system and method A system for reading substrate carriers that includes at least one overhead transport vehicle (OHT) utilizing at least one device for at least one of sensing and/or reading a substrate carrier, and/or wafers arranged therein, when the substrate carrier is proximate ... | 08/09/2011 |
| 7983368 | Systems and arrangements for clock and data recovery in communications A sampling clock signal controller for receivers of digital data is disclosed. Specific bit patterns of a data waveform can be identified, and stored time samples of the waveform that correspond to the specific bit patterns can be analyzed to improve the timing of a... | 07/19/2011 |
| 7968910 | Complementary field effect transistors having embedded silicon source and drain regions A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than sil... | 06/28/2011 |
| 7962234 | Multidimensional process window optimization in semiconductor manufacturing A method for optimizing multiple process windows in a semiconductor manufacturing process is disclosed. The method comprises performing dependent variable composition on a plurality of dependent variables. Metrology data is joined with the dependent variables, and t... | 06/14/2011 |
| 7956417 | Method of reducing stacking faults through annealing Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a fir... | 06/07/2011 |
| 7955952 | Crackstop structures and methods of making same An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to res... | 06/07/2011 |
| 7940846 | Test circuit for serial link receiver A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to th... | 05/10/2011 |
| 7936208 | Bias circuit for a MOS device A method and circuit for providing a bias voltage to a MOS device is disclosed. The method and circuit comprise utilizing at least one diode connected circuit to provide a voltage that tracks process, voltage and temperature variations of a semiconductor device. The... | 05/03/2011 |
| 7936153 | On-chip adaptive voltage compensation Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. These measurement circuits are connected to a voltage regulation circuit that provides the integrated circuit voltage source. These measurement circuits pro... | 05/03/2011 |
| 7923840 | Electrically conductive path forming below barrier oxide layer and integrated circuit Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path ... | 04/12/2011 |
| 7922796 | Chemical and particulate filters containing chemically modified carbon nanotube structures A carbon nanotube filter. The filter including a filter housing; and chemically active carbon nanotubes within the filter housing, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactiv... | 04/12/2011 |
| 7919819 | Interconnect components of a semiconductor device Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted... | 04/05/2011 |
| 7916820 | Systems and arrangements for clock and data recovery in communications A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extract... | 03/29/2011 |
| 7915691 | High density SRAM cell with hybrid devices Hybrid SRAM circuit, hybrid SRAM structures and method of fabricating hybrid SRAMs. The SRAM structures include first and second cross-coupled inverters coupled to first and second pass gate devices. The pull-down devices of the inverters are FinFETs while the pull-... | 03/29/2011 |
| 7904269 | Overhead traveling vehicle testing and calibration A method, system and test fixture for allowing testing and calibration of various operation parameters of an overhead traveling vehicle (hereinafter “OTV”) are disclosed. The invention implements a test fixture that includes a rotatable bearing set for rotatably... | 03/08/2011 |
| 7895454 | Instruction dependent dynamic voltage compensation A method for compensating for dynamic IR (voltage) drop for instruction execution. In a data processing system having a memory, and a central processing unit (CPU), where the CPU includes an adaptive power supply, a method is provided for determining the power requi... | 02/22/2011 |
