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| Number | Title | Issue Date |
| 7831873 | Method and apparatus for detecting sudden temperature/voltage changes in integrated circuits An integrated circuit is used to monitor and process parametric variations, such as temperature and voltage variations. An integrated circuit may include a temperature-sensitive oscillator circuit and a temperature-insensitive oscillator circuit, and frequency diffe... | 11/09/2010 |
| 7673267 | Method and apparatus for reducing jitter in an integrated circuit Methods and circuits to reduce jitter in a design block including partitioning the design block. A circuit design is partitioned into multiple partitioned design blocks performing the same task as the original circuit deign. In one embodiment, a core clock signal is... | 03/02/2010 |
| 7635997 | Circuit for and method of changing a frequency in a circuit The circuits and methods of the various embodiments of the present invention enable changing the frequency of a frequency synthesizer. According to one embodiment, a method of changing a frequency of a clock signal generated by a frequency synthesizer comprises the ... | 12/22/2009 |
| 7622948 | Parallel configuration of programmable devices A system for configuring a plurality of programmable devices may include an external memory, a master programmable device, and at least one slave programmable device. The programmable devices may have a parallel data bus connected in a daisy chain fashion. The progr... | 11/24/2009 |
| 7619486 | Method for detecting and compensating for temperature effects An integrated circuit fabricated in a multiple oxide process can be used to provide a temperature-insensitive circuit. The temperature-insensitive circuit can be a ring oscillator; this ring oscillator can be used as a low-cost integrated reference frequency to moni... | 11/17/2009 |
| 7576557 | Method and apparatus for mitigating one or more event upsets A method of configuring an integrated circuit having programmable logic including the steps of generating a configuration bitstream in accordance with a configuration setup, storing the configuration bitstream into a portion of a memory, configuring the programmable... | 08/18/2009 |
| 7574240 | Power estimation for mobile devices Method for power estimation for mobile devices for content downloading is described. More particularly, likelihood of download success is determined responsive to user selection of downloadable content after establishment of a connection between a mobile device and ... | 08/11/2009 |
| 7573295 | Hard macro-to-user logic interface A hard macro-to-user logic interface of an integrated circuit is described. The integrated circuit includes a core as an application specific circuit block with a transaction interface of a first bit width and includes programmable logic capable of being programmed ... | 08/11/2009 |
| 7546408 | Method and apparatus for communication within a programmable device using serial transceivers Method and apparatus for communication within a programmable logic device using serial transceivers is described. In an example, an integrated circuit includes a first module and a second module. The first module and the second module each include a transceiver coup... | 06/09/2009 |
| 7546394 | Management of configuration data by generating a chain description data set that specifies an order of configuration chain for multi-device systems Methods and apparatus are disclosed for managing configuration data for a system. In various embodiments, a chain description data set is generated to specify an order in a configuration chain of configurable devices in the system and identify configuration data set... | 06/09/2009 |
| 7539848 | Configurable logic fabric including two fixed logic processors with individual interface to receive availability signal from custom operation code configured processor A system is disclosed comprising a logic circuit in an integrated circuit device, wherein the logic circuit comprises a logic fabric that includes a plurality of configurable logic blocks, switching blocks, and input/output blocks, wherein the logic fabric is config... | 05/26/2009 |
| 7539241 | Packet detector for a communication system Method and apparatus for packet detection is described. More particularly, a signal having sub-signals is received. The signal is quantized (“re-quantized”) to provide a quantized signal to processing units, where the quantized signal is a sequence of samples. A... | 05/26/2009 |
| 7535213 | Method and system for prediction of atmospheric upsets in an integrated circuit Prediction of a rate of atmospheric upsets in an integrated circuit (IC) is described. In one embodiment, a first rate of atmospheric upsets is measured in a plurality of ICs of a first type. Within a beam of atomic particles, a second rate of beam upsets of at leas... | 05/19/2009 |
| 7525362 | Circuit for and method of preventing an error in a flip-flop A circuit for preventing an error in a flip-flop is disclosed. The circuit comprises an input circuit for receiving input data; a circuit for generating true and complement data associated with each of the input data and redundant data at predetermined nodes of the ... | 04/28/2009 |
| 7516437 | Skew-driven routing for networks A method of generating a low-skew network for a circuit design can include routing connections between a source and a plurality of loads of the network, determining a delay for at least one routed connection, and accepting the routed connections if the delay of each... | 04/07/2009 |
| 7515668 | Data and/or clock recovery circuits with sampling offset correction A method for correcting sampling offset of a clock and data recovery circuit begins for consecutive data bits having a transition there between by sampling, using an edge sampling point, the transition to produce a sampled transition. The method continues by determi... | 04/07/2009 |
| 7515664 | Method of recovering data in asynchronous applications Data is recovered in an asynchronous environment where a sampling clock is generated internally, and is not externally frequency locked, by using programmable delay modules each providing a number of delay tap outputs. To recover data, two of the delay modules are u... | 04/07/2009 |
| 7512871 | Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic out... | 03/31/2009 |
| 7509608 | Integrated system noise management—clock jitter A method for estimating jitter of an integrated circuit design is described. A description of logic blocks of the integrated circuit design is obtained. A description of input/output blocks of the integrated circuit design is obtained. A first type of a first jitter... | 03/24/2009 |
| 7506210 | Method of debugging PLD configuration using boundary scan Methods and tools for detecting and correcting problems arising in the configuration process of a programmable logic device are described. An analyzer is used to aid a user in debugging the configuration process. The analyzer can access the programmable logic device... | 03/17/2009 |
| 7504891 | Initialization circuit for a phase-locked loop Integrated circuit including a phase-locked loop (PLL) circuit having a first mode and a second mode of operation. Operating the PLL circuit in the first mode may generate a constant frequency responsive to a programmable bias. Operating the PLL circuit in the secon... | 03/17/2009 |
| 7502433 | Bimodal source synchronous interface Method and apparatus for a bimodal source synchronous interface for a receiver module is described. A first input cell with a first delay chain and a first register block is provided for receipt of a forwarded clock signal by the first delay chain. A second input ce... | 03/10/2009 |
| 7500060 | Hardware stack structure using programmable logic A hardware stack (HSTACK) structure using programmable logic can include a look-up table (LUT) random access memory (RAM) circuit and circuitry within the LUT RAM circuit for propagating data upwards and downwards. The hardware structure can be arbitrarily assembled... | 03/03/2009 |
| 7498836 | Programmable low power modes for embedded memory blocks A PLD (700) includes a plurality of logic blocks (701), a plurality of high gating circuits (702) coupled between corresponding logic blocks (701) and a supply voltage (VDD), a plurality of low gating circuits (703) coupled between... | 03/03/2009 |
| 7498835 | Implementation of low power standby modes for integrated circuits A PLD (200) includes a power management unit (PMU 210) that selectively implements one or more different power-reduction techniques in response to power configuration signals (PC). By manipulating the PC signals, the PMU can independently enable/disabl... | 03/03/2009 |
| 7480361 | Phase lock detector Method and apparatus for phase lock detection is described. More particularly, a phase lock detection circuit (20) includes a synchronization circuit (23) coupled to receive a reference signal (31) and configured to provide a derivative signal (... | 01/20/2009 |
| 7475297 | Efficient method for computing clock skew without pessimism The present invention includes a method and an apparatus, in one embodiment, in the form of an integrated circuit and programmable fabric design tool, for calculating skew in a manner that does not include unnecessary skew values, resulting in a skew value without p... | 01/06/2009 |
| 7472370 | Comparing graphical and netlist connections of a programmable logic device A processor-implemented method is provided for comparing connections in a graphical representation of a programmable logic device (PLD) design to connections in a netlist that describes the PLD design. The netlist and an identification of each tile are input. For ea... | 12/30/2008 |
| 7472365 | Method for computing hold and setup slack without pessimism The present invention includes a method and an apparatus, in one embodiment, in the form of an integrated circuit and programmable fabric design tool, for calculating skew in a manner that does not include unnecessary skew values, resulting in a skew value without p... | 12/30/2008 |
| 7468615 | Voltage level shifter A high-speed, area-efficient level shifter includes transistors having a variety of oxide thicknesses. The level shifter has a protection circuit stage, and a current mirror stage that allows the level shifter to perform over a wide voltage range at a high frequency... | 12/23/2008 |
| 7460848 | Differential signal strength detector A signal detection circuit includes a first signal multiplier operably coupled to square an input signal, a second signal multiplier operably coupled to square a reference signal, and a filter module operably coupled to produce a digital output representative of the... | 12/02/2008 |
| 7452765 | Single event upset in SRAM cells in FPGAs with high resistivity gate structures SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening se... | 11/18/2008 |
| 7454587 | Method and apparatus for memory management in an integrated circuit Method and apparatus for managing memory logic is described. In one example, user logic, virtual port logic, and a processor are provided. The user logic is configured to provide allocation requests for the memory logic, access requests for the memory logic, and de-... | 11/18/2008 |
| 7440454 | Packet reshuffler and method of implementing same A packet reshuffler and a method of implementing the same is described. In one example, a digital logic circuit in a transmitter for sending packets stored in a set of buffers includes circular shift register logic, encoder logic, selection logic, and combinatorial ... | 10/21/2008 |
| 7440530 | Circuit for and method of optimizing the transmission of data on a communication channel A circuit for optimizing the transmission of data on a communication channel is disclosed. According to one embodiment of the invention, a circuit comprises a transmitter circuit having a programmable output characteristic and being coupled to a transmission media. ... | 10/21/2008 |
| 7436726 | Circuit for and method of reading data in an asynchronous FIFO including a backup address circuit for re-reading data A circuit for enabling reading data in an asynchronous FIFO memory of an integrated circuit is described. The circuit comprises a memory storing data in a plurality of slots having a corresponding plurality of addresses. A write address counter stores a write addres... | 10/14/2008 |
| 7426251 | High speed transceiver operable to receive lower data rate transmissions A high speed transceiver operable to receive lower data rate transmissions includes an oversampling module and a data recovery system. The oversampling module is operably coupled to oversample a unique alignment sequence and data of a data stream received at a first... | 09/16/2008 |
| 7423452 | Integrated circuit including a multiplexer circuit An integrated circuit including a multiplexer circuit and numerous memory cells are coupled to one another for improved performance. The multiplexer circuit includes a first input terminal and a second input terminal respectively coupled to an output of a first memo... | 09/09/2008 |
| 7420392 | Programmable gate array and embedded circuitry initialization and processing Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting... | 09/02/2008 |
| 7397272 | Parallel configuration of programmable devices A system for configuring a plurality of programmable devices may include an external memory, a master programmable device, and at least one slave programmable device. The programmable devices may have a parallel data bus connected in a daisy chain fashion. The progr... | 07/08/2008 |
