Quotables
"Everyone acquainted with the subject will recognize it as a conspicuous failure."
Henry Morton, president of the Stevens Institute of Technology ; Said in 1880 about the light bulb
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 5675546 | On-chip automatic procedures for memory testing The on-chip endurance test (Autocycle) and the parametric characterization test (Auto VccMax/Min) of this invention save test time and hardware by performance automatically on the memory chip upon transmittal of a single command (CONTROL CODE) to the chip... | 10/07/1997 |
| 5668769 | Memory device performance by delayed power-down The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablem... | 09/16/1997 |
| 5659500 | Nonvolatile memory array with compatible vertical source lines A nonvolatile memory array has a plurality of diffused horizontal source lines (17), each source line (17) positioned between a pair of parallel horizontal stack conductors (ST). The plurality of the diffused horizontal source lines (17) are connected to ... | 08/19/1997 |
| 5657268 | Array-source line, bitline and wordline sequence in flash operations In a multi-sector nonvolatile memory array in which each memory cell has a drain coupled to a bitline, each memory cell of each sector has a source coupled to a common array-source line, each memory cell in a row of the first sector has a control gate cou... | 08/12/1997 |
| 5654219 | Annealed poly-silicide etch process A method for forming poly-silicide conductors (CG,GAP) on a semiconductor device (10) includes forming a layer (14) of doped polysilicon over a region of the device (10), then depositing a layer (15) of refractory metal on the layer (14) of doped polysili... | 08/05/1997 |
| 5646894 | Smart boost circuit for low voltage flash EPROM The circuit of this invention improves significantly the programming speed of a Flash EPROM. The circuit includes a detector circuit (DC) using a pre-charge capacitor (C1), capacitor dividers [(C1/(C1+C2) and C3/(C2+C3)] and a voltage comparator (COMP) to... | 07/08/1997 |
| 5646887 | Sense amplifier with pre-charge circuit and low-voltage operation mode Low-voltage-correcting bias circuitry for a sense amplifier includes first, second and third N-channel transistors. The channel of the first transistor couples a current mirror to the input terminal of the amplifier and the gate of the second transistor, ... | 07/08/1997 |
| 5636226 | Fault sensing circuit and method A fault sensing circuit for detecting the state of at least one latch controlled by at least one control signal is provided. The circuit comprises an additional latch also controlled by the same control signal and receiving an input of a known value. The ... | 06/03/1997 |
| 5636162 | Erase procedure A procedure for erasing a Flash EPROM array (AR) includes applying a series of erase pulses to all of the subarrays (S1, S2, etc.) of a Flash EPROM array (AR) simultaneously. Between each erase pulse, the memory cells (10) of each sub array (S1, S2, etc.)... | 06/03/1997 |
| 5604150 | Channel-stop process for use with thick-field isolation regions in triple-well structures To ensure proper electrical insulation under thick-field isolation regions (23) grown in triple-well structures, the channel-stop impurity (30) is implanted using multiple doses at different energies, depending on the oxide thickness of the thick-field is... | 02/18/1997 |
| 5596528 | Method of using source bias to raise threshold voltages and/or to compact threshold voltages The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method... | 01/21/1997 |
| 5576992 | Extended-life method for soft-programming floating-gate memory cells An extended-life method for soft-programming at least one floating gate memory cell (10) includes connecting the substrate and the source (11) to a reference voltage, then applying to the control gate (13) a soft-programming voltage, the soft-programming ... | 11/19/1996 |
| 5576567 | Vertical memory cell array and method of fabrication A vertical memory cell EPROM array (FIGS. 1, 1a and 1b) uses a vertical floating gate memory cell structure that can be fabricated with reduced cell area and channel length. The vertical memory cell memory array includes multiple rows of buried layers tha... | 11/19/1996 |
| 5565371 | Method of making EPROM with separate erasing and programming regions An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (21). Each memory cell includes a source region (11) and a drain region (12) formed in a shared drain-column line (1... | 10/15/1996 |
| 5528543 | Sense amplifier circuitry Sense amplifier circuitry (SC) includes a differential amplifier (A) having a reference input and a memory input. The output of a first sense amplifier (SA1) is coupled to the reference input of the differential amplifier (A) and to the input of a second ... | 06/18/1996 |
| 5526315 | Biasing circuit and method to achieve compaction and self-limiting erase in flash EEPROMS The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells (10). Each cell includes a control gate (14), a source (11) and a drain (12). The me... | 06/11/1996 |
| 5523249 | Method of making an EEPROM cell with separate erasing and programming regions An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region be... | 06/04/1996 |
| 5508544 | Three dimensional FAMOS memory devices Memory cell transistors are provided in which column structures (12a, 14a) are formed at the face of a semiconductor substrate (10). Floating gates (46) and control gates (52) are formed adjacent to the column structures (12a, 14a). The floating gates (46... | 04/16/1996 |
| 5504708 | Flash EEPROM array with P-tank insulated from substrate by deep N-tank In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated mem... | 04/02/1996 |
| 5491809 | Smart erase algorithm with secure scheme for flash EPROMs A method for erasing blocks of a non-volatile memory includes detecting whether a block is in at least one of an erased state or a state secured from erasure; then setting a flag register at a first level for each block detected to be in at least one of a... | 02/13/1996 |
| 5491660 | On-chip operation control for memories The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a ... | 02/13/1996 |
| 5469383 | Memory cell array having continuous-strip field-oxide regions A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silic... | 11/21/1995 |
| 5467306 | Method of using source bias to increase threshold voltages and/or to correct for over-erasure of flash eproms The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method... | 11/14/1995 |
| 5450417 | Circuit for testing power-on-reset circuitry The power-on-reset test circuit of this invention includes two imbalanced latches to detect the occurrence of a transient power-on-reset signal. The occurrence of a transient power-on-reset signal is latched for later verification during circuit testing. ... | 09/12/1995 |
| 5450357 | Level shifter circuit A level shifter circuit 150 for selecting different voltage levels for programming memory cells 10 is provided. The level shifter 150 has an input 152 connected to a control circuitry and an output 154 connected to memory cells 10. The level shifter 150 i... | 09/12/1995 |
| 5428578 | Biasing circuit and method to achieve compaction and self-limiting erase in flash EEPROMs The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells (10). Each cell includes a control gate (14), a source (11 ) and a drain (12). The m... | 06/27/1995 |
| 5424992 | Method and device for detecting and controlling an array source signal discharge for a memory erase operation An array source signal discharge controller device (10) includes a pulse converter circuit (12) that receives an erase pulse signal (ERPULSE). The pulse converter circuit (12) converts the erase pulse signal (ERPULSE) into a pulse control signal (ERPCL) t... | 06/13/1995 |
| 5422590 | High voltage negative charge pump with low voltage CMOS transistors A system for erasing a memory array in a memory has a supply voltage and a negative charge pump. The negative charge pump system includes (a) circuitry to select a memory array to be erased; (b) for circuitry to switch on the supply voltage Vnn for the ch... | 06/06/1995 |
| 5420060 | Method of making contract-free floating-gate memory array with silicided buried bitlines and with single-step defined floating gates A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for par... | 05/30/1995 |
| 5418741 | Virtual ground memory cell array A memory cell array for a nonvolatile memory device having single-transistor cells (10). Row lines (15) connect the control gates of each row of cells. Column lines (17) connect the drain regions (11) and source regions (12) of columns of cells, such that... | 05/23/1995 |
| 5412603 | Method and circuitry for programming floating-gate memory cell using a single low-voltage supply The drain-to-source voltage and current for programming a selected nonvolatile memory cell 10 are achieved efficiently by pumping the source 11 of a selected cell 11 to a voltage less than the voltage VSS at the reference-voltage terminal of the memory ce... | 05/02/1995 |
| 5411908 | Flash EEPROM array with P-tank insulated from substrate by deep N-tank In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated mem... | 05/02/1995 |
| 5397946 | High-voltage sensor for integrated circuits The CMOS high-voltage sensor circuit has a voltage reference including, for example, of four N-channel MOS transistors; one pass-gate P-channel transistor; one current-mirror P-channel MOS transistor; and a conventional high-voltage sensor including, for ... | 03/14/1995 |
| 5396115 | Current-sensing power-on reset circuit for integrated circuits The power-on reset circuit of this invention includes a current-sensing circuit, a pulse-stretching circuit, and a voltage-reference circuit. The voltage-reference circuit consists, for example, of one N-Channel and one P-Channel MOS transistor. The circu... | 03/07/1995 |
| 5392248 | Circuit and method for detecting column-line shorts in integrated-circuit memories The column-line short detection circuit of this invention includes a special test circuit that turns off wordlines (15), a N-channel transistor (23) for each column line (18), a decoder (19a) that uses only the least significant column address (20d) for i... | 02/21/1995 |
| 5371706 | Circuit and method for sensing depletion of memory cells The circuit and method of this invention provide for rapid and reliable detection of depleted or nearly-depleted cells in a column. The circuit is formed on the substrate of a nonvolatile, integrated-circuit memory including rows and columns of memory cel... | 12/06/1994 |
| 5371031 | Method of making EEPROM array with buried N+ windows and with separate erasing and programming regions An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region be... | 12/06/1994 |
| 5354703 | EEPROM cell array with tight erase distribution An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source (11) and a drain (12), with a corresponding channel (Ch) between. A control... | 10/11/1994 |
| 5340768 | Method of fabricating self-aligned field-plate isolation between control electrodes The structure and method of this invention provide, for example, electrical isolation between active elements in adjacent rows and/or columns of an integrated circuit by use of a self-aligned field-plate conductor formed over and insulated from the substr... | 08/23/1994 |
| 5334550 | Method of producing a self-aligned window at recessed intersection of insulating regions An integrated circuit structure and process relating to a self-aligned window at the recessed junction of two insulating regions formed on the surface of a semiconductor body. The window may include a trench forming an isolation region between doped semic... | 08/02/1994 |
