Linden; Gerald E., Rostoker; Michael D. - US Patent Attorneys and Agents

Attorney: Linden; Gerald E., Rostoker; Michael D.

Number of patents: 33
Last date: May 17, 1994

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Number	Title	Issue Date
5312770	Techniques for forming isolation structures Various techniques of forming isolation structures between adjacent diffusion regions are disclosed. In one technique, a thermally-grown oxide isolation structure is gouged out, and subsequent poly extending into the gouged out isolation structure is subs...	05/17/1994
5310455	Techniques for assembling polishing pads for chemi-mechanical polishing of silicon wafers A technique for mounting polishing pads to a platen in chemi-mechanical semiconductor wafer polishing apparatus is disclosed. A lower pad is mounted to the platen, and is trimmed to the size of the platen. An upper pad is mounted to the lower pad, and is ...	05/10/1994
5307559	Method of providing a capacitor within a semiconductor device package A capacitor is disposed within a semiconductor device assembly atop a plastic layer pad, beneath which passes a pair of leads connected to a semiconductor device. The capacitor is connected to the pair of leads, such as by soldering, spot welding or condu...	05/03/1994
5299730	Method and apparatus for isolation of flux materials in flip-chip manufacturing A preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure, and establishes a minimum gap between the chip(s) and the substrate. Liquid flux may be applied to the preformed planar structure in order that flux...	04/05/1994
5298110	Trench planarization techniques Various techniques for quantifying polishing performance are disclosed, and provide insight on the progression from a planarization regime to a smoothing regime to a blanket polish back regime, as well as providing a single, definable parameter (Quality C...	03/29/1994
5290396	Trench planarization techniques Various techniques for quantifying polishing performance are disclosed, and provide insight on the progression from a planarization regime to a smoothing regime to a blanket polish back regime, as well as providing a single, definable parameter (Quality C...	03/01/1994
5287247	Computer system module assembly A computer system module includes a central processing unit (CPU), a floating-point accelerator (FPA), a read/write buffer (RWB), cache memory, a clock generator, buffers, and reset logic. The signal composition of the module includes: Configuration Buffe...	02/15/1994
5286519	Fluid dispersion head A fluid distribution head of this invention includes a chamber for fluid flow including a perforated plate. The perforated plate is internally supported by a structural support to avoid deformation of the plate....	02/15/1994
5284797	Semiconductor bond pads Bond pad lift problems encountered during bonding are alleviated by providing an upper bond pad, a lower bond pad and an insulating component between the upper and lower bond pads. At least one opening is provided through the insulating component, extendi...	02/08/1994
5278769	Automatic logic model generation from schematic data base An automatic logic-model generation system operates on a schematic database and produces logic models incorporating accurate timing information. A verification process is also performed whereby the model is automatically verified for accuracy....	01/11/1994
5275326	Guide hole sleeves for boat transports supporting semiconductor device assemblies Damage to the pins and ceramic body of pin grid array type semiconductor device assemblies is avoided by providing ceramic bushings in the pin-receiving holes of a boat transport. The bushings elevate the package body above the platform surface of the boa...	01/04/1994
5262927	Partially-molded, PCB chip carrier package A dambar-less leadframe is sandwiched between two printed circuit boards (PCBs). The PCBs form a major portion of the package body, and isolate the leadframe leads from plastic molding compound. In one embodiment, an upper PCB (substrate) is formed as a s...	11/16/1993
5260514	Wire bonder and vacuum pedestal workholder for same A fully-populated Pin Grid Array (PGA) is vacuum-chucked to a pedestal, without mechanical clamping. The pedestal includes a cylindrical shaft having a vacuum passageway extending its length, and a vacuum reservoir block mounted atop the shaft, and an ali...	11/09/1993
5254940	Testable embedded microprocessor and method of testing same A technique of gaining direct access to the inputs and outputs of an embedded microprocessor, otherwise buried behind additional logic, is disclosed. Multiplexers are provided for at least the embedded microprocessor inputs and outputs. In a test mode, th...	10/19/1993
5249281	Testable RAM architecture in a microprocessor having embedded cache memory A microprocessor with embedded cache memory is disclosed. In a "test mode" of operation, caches are accessed directly from the memory interface signals. Direct writing and reading to/from the instruction and data caches allows the testing of the functiona...	09/28/1993
5248903	Composite bond pads for semiconductor devices Bond pad lift problems encountered during bonding are alleviated by providing an upper bond pad, a lower bond pad and an insulating component between the upper and lower bond pads. At least one opening is provided through the insulating component, extendi...	09/28/1993
5248625	Techniques for forming isolation structures Various techniques of forming isolation structures between adjacent diffusion regions are disclosed. In one technique, a thermally-grown oxide isolation structure is gouged out, and subsequent poly extending into the gouged out isolation structure is subs...	09/28/1993
5247153	Method and apparatus for in-situ deformation of a surface, especially a non-planar optical surface The surface of an optical element, such as the taking lens in semiconductor photolithographic apparatus, is deformed, in situ, by applying heat to the surface. A recipe for applying the heat to a selected area of the lens surface is developed by either me...	09/21/1993
5245790	Ultrasonic energy enhanced chemi-mechanical polishing of silicon wafers A technique for chemi-mechanical polishing of semiconductor wafers using ultrasonic energy is disclosed. A transducer is mounted in the polishing system, either to a platen to which the polishing pad is mounted, or to a carrier to which the semiconductor ...	09/21/1993
5242536	Anisotropic polysilicon etching process An anisotropic polysilicon etching process in Cl2 /HBr/He is disclosed. The use of HBr allows etching to occur under high poly:oxide selectivity conditions (e.g., above 40:1) that would otherwise produce lateral etching of the poly under the ph...	09/07/1993
5231601	Digital multiplier based upon a regularly structured sum of products adder array for partial product reduction A digital multiplier is configured from a number of identical circuit "slices" with interconnecting signals arranged such that the need for large wiring channels is eliminated. The resulting multiplier, a hybrid of tree and array multipliers, has many of ...	07/27/1993
5227663	Integral dam and heat sink for semiconductor device assembly A metallic or ceramic dam structure surrounding a semiconductor die in a semiconductor device assembly is disclosed. The dam structure forms a cavity containing a potting compound encapsulating the die. The dam structure may also be provided with a flat l...	07/13/1993
5227332	Methods of plating into holes and products produced thereby In the plating of articles, particularly the filling of via-holes (16) in the manufacture of semiconductor devices, a catalyst, for example palladium, is incorporated throughout the body of material (12) to which plating is to be effected, as compared wit...	07/13/1993
5226048	At-speed testing of core logic A technique for at-speed testing of the core logic of a digital integrated circuit device is disclosed. Test patterns are applied to the circuit inputs while applying a "burst" of three clock pulses followed by a "dead cycle"to the pipeline stages between...	07/06/1993
5222030	Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the inten...	06/22/1993
5220192	Radiation hardened CMOS structure using an implanted P guard structure and method for the manufacture thereof A radiation hardened NMOS transistor structure suited for application to radiation hardened CMOS devices, and the method for manufacturing it is disclosed. The new transistor structure is characterized by "P" doped guard bands running along and immediatel...	06/15/1993
5217566	Densifying and polishing glass layers A glass passivation layer is deposited, densified and polished. Thereby an underlying wafer containing substantially defined devices is exposed to a temperature cycle that is sufficient for densification of the glass, and no more. Reflow and its attendant...	06/08/1993
5211324	Composite boat transport providing clipless securement of semiconductor device assembly to boat transport, and of lid to package body A magnet is disposed in proximity to an un-lidded semiconductor package being assembled. When a ferrous lid is placed over the package opening, the magnetic field holds the lid in place, and also holds the package on an assembly boat carrying the package ...	05/18/1993
5210683	Recessed chip capacitor wells with cleaning channels on integrated circuit packages Wells are formed in an external surface of a semiconductor device package body. Capacitors are disposed within the wells at least partially, and preferably fully within the body. Cleaning channels are formed underneath the capacitors, for removing residua...	05/11/1993
5204829	Interleaving operations in a floating-point numeric processor A pipelined floating point multiplier is disclosed having the capability of interleaving floating point multiplication with iterative floating point operations (calculations), such as division and square-root taking, by making use of idle stages (pipeline...	04/20/1993
5200642	Internal capacitor arrangement for semiconductor device assembly A capacitor is disposed within a semiconductor device assembly atop a plastic layer pad, beneath which passes a pair of leads connected to a semiconductor device. The capacitor is connected to the pair of leads, such as by soldering, spot welding or condu...	04/06/1993
5197183	Modified lead frame for reducing wire wash in transfer molding of IC packages In a leadframe supporting a semiconductor device, the tiebar adjacent the mold gate is kinked, or cut and bent, to form a baffle shielding bond wires connecting the semiconductor device to the leadframe from damage by a jet of incoming molding compound. W...	03/30/1993
5055871	Method and apparatus for enhancing illumination uniformity in wafer steppers using photochromic glass in the optical path Enhanced uniformity of illumination is achieved in photolithography by interposing photochromic glass in the light path between the illuminator light source and a semiconductor wafer. In one embodiment of the invention, the photochromic glass is disposed ...	10/08/1991

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Attorney: Linden; Gerald E., Rostoker; Michael D.