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| Number | Title | Issue Date |
| 7642569 | Transistor structure with minimized parasitics and method of fabricating the same A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrin... | 01/05/2010 |
| 7573115 | Structure and method for enhancing resistance to fracture of bonding pads The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in b... | 08/11/2009 |
| 7573104 | CMOS device on hybrid orientation substrate comprising equal mobility for perpendicular devices of each type Embodiments herein present device, method, etc. for a hybrid orientation scheme for standard orthogonal circuits. An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate, comprising first areas having a first crystalline orient... | 08/11/2009 |
| 7564081 | finFET structure with multiply stressed gate electrode A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and ... | 07/21/2009 |
| 7560761 | Semiconductor structure including trench capacitor and trench resistor A structure and a method for fabrication of the structure use a capacitor trench for a trench capacitor and a resistor trench for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench has a linewidth dimen... | 07/14/2009 |
| 7544994 | Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the ov... | 06/09/2009 |
| 7521763 | Dual stress STI The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transisto... | 04/21/2009 |
| 7504696 | CMOS with dual metal gate Embodiments herein present a structure and method to make a CMOS with dual metal gates. Specifically, the CMOS comprises a first gate comprising a first metal and a second gate comprising a second metal. The first gate comprises a portion of a first transistor that ... | 03/17/2009 |
| 7494938 | Advanced low dielectric constant organosilicon plasma chemical vapor deposition films A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactio... | 02/24/2009 |
| 7494891 | Trench capacitor with void-free conductor fill A method forms a node dielectric in a bottle shaped trench and then deposits an initial conductor within the lower portion of the bottle shaped trench, such that a void is formed within the initial conductor. Next, the method forms an insulating collar in the upper ... | 02/24/2009 |
| 7491964 | Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjace... | 02/17/2009 |
| 7491617 | Transistor structure with minimized parasitics and method of fabricating the same A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrin... | 02/17/2009 |
| 7491563 | Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjace... | 02/17/2009 |
| 7485510 | Field effect device including inverted V shaped channel region and method for fabrication thereof A semiconductor structure includes a semiconductor layer that includes an inverted V shaped channel region that allows avoidance of a raised source/drain region within the semiconductor structure. In one embodiment, a generally conventional gate electrode is located... | 02/03/2009 |
| 7482209 | Hybrid orientation substrate and method for fabrication of thereof A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the ex... | 01/27/2009 |
| 7479633 | Methodology for critical dimension metrology using stepper focus monitor information A method of producing an accurate critical dimension measurement comprises navigating to a critical dimension structure, performing a scanning electron microscope focusing, performing a final location alignment, acquiring waveform data, analyzing the data to determi... | 01/20/2009 |
| 7475368 | Deflection analysis system and method for circuit design A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for ea... | 01/06/2009 |
| 7466010 | Bipolar transistor having self-aligned silicide and a self-aligned emitter contact border The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do n... | 12/16/2008 |
| 7459743 | Dual port gain cell with side and top gated read transistor A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible wi... | 12/02/2008 |
| 7454687 | Method and infrastructure for recognition of the resources of a defective hardware unit A system and method of recognizing resources of a computer comprising a system serial number and a broken hardware unit comprising a non-volatile memory unit and enablement definition data relating to functions of the broken hardware unit, wherein the method compris... | 11/18/2008 |
| 7446036 | Gap free anchored conductor and dielectric structure and method for fabrication thereof A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the fi... | 11/04/2008 |
| 7446005 | Manufacturable recessed strained RSD structure and process for advanced CMOS A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer oxygen and carb... | 11/04/2008 |
| 7402870 | Ultra shallow junction formation by epitaxial interface limited diffusion A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top... | 07/22/2008 |
| 7381623 | Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second ga... | 06/03/2008 |
| 7361973 | Embedded stressed nitride liners for CMOS performance improvement The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner provid... | 04/22/2008 |
| 7358130 | Method for monitoring lateral encroachment of spacer process on a CD SEM A process implementing steps for determining encroachment of a spacer structure in a semiconductor device having thick and thin spacer regions, including a transition region formed therebetween. The method steps comprise: obtaining a line width roughness (LWR) measu... | 04/15/2008 |
| 7339230 | Structure and method for making high density mosfet circuits with different height contact lines Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits include a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate lay... | 03/04/2008 |
| 7288362 | Immersion topcoat materials with improved performance A topcoat material for applying on top of a photoresist material is disclosed. The topcoat material comprises at least one solvent and a polymer which has a dissolution rate of at least 3000 Å/second in aqueous alkaline developer. The polymer contains a hexafluoro... | 10/30/2007 |
| 7268049 | Structure and method for manufacturing MOSFET with super-steep retrograded island The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protecte... | 09/11/2007 |
| 7253070 | Transistor structure with minimized parasitics and method of fabricating the same A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrin... | 08/07/2007 |
| 7229885 | Formation of a disposable spacer to post dope a gate conductor A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on s... | 06/12/2007 |
| 7202564 | Advanced low dielectric constant organosilicon plasma chemical vapor deposition films A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactio... | 04/10/2007 |
| 7172431 | Electrical connector design and contact geometry and method of use thereof and methods of fabrication thereof A probe or an electrical connector comprises a substrate with a surface having a plurality of electrical contact locations. A shaped elongated electrical conductor has a first end coupled to one of the electrical contact locations and a second end thereof which proj... | 02/06/2007 |
| 7144769 | Method to achieve increased trench depth, independent of CD as defined by lithography A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial... | 12/05/2006 |
| 7115955 | Semiconductor device having a strained raised source/drain A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer comprising oxyg... | 10/03/2006 |
| 7105398 | Method for monitoring lateral encroachment of spacer process on a CD SEM A process implementing steps for determining encroachment of a spacer structure in a semiconductor device having thick and thin spacer regions, including a transition region formed therebetween. The method steps comprise: obtaining a line width roughness (LWR) measu... | 09/12/2006 |
| 7071103 | Chemical treatment to retard diffusion in a semiconductor overlayer The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the... | 07/04/2006 |
| 6979884 | Bipolar transistor having self-aligned silicide and a self-aligned emitter contact border The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do n... | 12/27/2005 |
| 6967375 | Reduction of chemical mechanical planarization (CMP) scratches with sacrificial dielectric polish stop Disclosed in a method of planarizing a silicon on insulator (SOI) structure. The invention performs a first chemical mechanical planarization (CMP) process on an insulator (e.g., oxide) layer. However, this first CMP process creates scratches on the insulator layer.... | 11/22/2005 |
| 6919146 | Planar reticle design/fabrication method for rapid inspection and cleaning A reticle has a transparent substrate, mask shapes on the substrate, a transparent material covering the mask shapes and an optional anti-reflective material over the transparent material. ... | 07/19/2005 |
