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| Number | Title | Issue Date |
| 7793163 | Method and system for extending the useful life of another system Disclosed are embodiments of a method and an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system ... | 09/07/2010 |
| 7684224 | Structure comprising 3-dimensional integrated circuit architecture, circuit structure, and instructions for fabrication thereof An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently opt... | 03/23/2010 |
| 7631236 | Hybrid built-in self test (BIST) architecture for embedded memory arrays and an associated method Disclosed are embodiments of a built-in self-test (BIST) architecture that incorporates a standalone controller that operates at a lower frequency to remotely perform test functions common to a plurality of embedded memory arrays. The architecture also incorporates ... | 12/08/2009 |
| 7619398 | Programmable on-chip sense line Disclosed herein is a system for controlling power supply voltage to an on-chip power distribution network. The system incorporates a programmable on-chip sensing network that can be selectively connected to the power distribution network at multiple locations. When... | 11/17/2009 |
| 7613047 | Efficient circuit and method to measure resistance thresholds The embodiments of the invention provide an apparatus, method, etc. for an efficient circuit and method to measure resistance. A sense line driver for an integrated circuit memory is provided, including a sense node that receives an experiment signal from an experim... | 11/03/2009 |
| 7505348 | Balanced and bi-directional bit line paths for memory arrays with programmable memory cells An improved memory system incorporates an array of memory cells that are subjected to minimal location dependent power variations and, optionally, allows for bi-directional random access of millions of bits. The system architecture provides a consistent amount of bi... | 03/17/2009 |
| 7504847 | Mechanism for detection and compensation of NBTI induced threshold degradation The embodiments of the invention provide an apparatus and method for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage a... | 03/17/2009 |
| 7495492 | Dynamic latch state saving device and protocol The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated... | 02/24/2009 |
| 7489204 | Method and structure for chip-level testing of wire delay independent of silicon delay Disclosed are a method and a structure for testing location-specific wire delay at a chip-level independent of silicon delay. The invention incorporates the use of a tester embedded in a metal layer of a chip. The tester comprises a ring oscillator that is selective... | 02/10/2009 |
| 7484423 | Integrated carbon nanotube sensors A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is a... | 02/03/2009 |
| 7487481 | Receiver circuit for on chip timing adjustment A structure for for maintaining signal integrity between integrated circuits residing on a printed circuit board. The structure has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the c... | 02/03/2009 |
| 7472320 | Autonomous self-monitoring and corrective operation of an integrated circuit Disclosed is a method and apparatus for autonomously self-monitoring and self-adjusting the operation of an integrated circuit device throughout the integrated circuit device's useful life. The invention periodically performs performance self-testing on the integrat... | 12/30/2008 |
| 7456674 | Clock generator having improved deskewer Disclosed is a clock generation circuit for generating a clock-out signal that has a fixed latency with respect to a clock-input signal. When multiple such clock generation circuits are utilized to feed clock signals to different digital logic circuits within an int... | 11/25/2008 |
| 7437620 | Method and system for extending the useful life of another system Disclosed are embodiments of a method and an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system ... | 10/14/2008 |
| 7403061 | Method of improving fuse state detection and yield in semiconductor applications Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection cir... | 07/22/2008 |
| 7397263 | Sensor differentiated fault isolation Disclosed is an apparatus and method for diagnostically testing circuitry within a device. The apparatus and method incorporate the use of energy (e.g., light, heat, magnetic, electric, etc.) applied directly to any location on the device that can affect the electri... | 07/08/2008 |
| 7397228 | Programmable on-chip sense line Disclosed herein is a system for controlling power supply voltage to an on-chip power distribution network. The system incorporates a programmable on-chip sensing network that can be selectively connected to the power distribution network at multiple locations. When... | 07/08/2008 |
| 7339364 | Circuit and method for on-chip jitter measurement An improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal, the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circu... | 03/04/2008 |
| 7284172 | Access method for embedded JTAG TAP controller instruction registers Disclosed is an integrated circuit chip structure that has a chip level test access port (TAP) controller and a plurality of embedded TAPs connected to the chip level TAP. Because the embedded TAPs have lengths that differ from the chip level TAP IR, and the embedde... | 10/16/2007 |
| 7254647 | Network for decreasing transmit link layer core speed A processor includes a core for providing speed reduction in communications between a transmission media and a processor having an upper link layer in a parallel-serial architecture. The core includes a lower logic layer, serial lanes connecting the logic layer to t... | 08/07/2007 |
| 7127560 | Method of dynamically controlling cache size A power saving cache and a method of operating a power saving cache. The power saving cache includes circuitry to dynamically reduce the logical size of the cache in order to save power. Preferably, a method is used to determine optimal cache size for balancing powe... | 10/24/2006 |
| 7111151 | Microprocessor including microcode unit that only changes the value of control signals required for the current cycle operation for reduced power consumption and method therefor A microprocessor, method and signal-bearing medium for storing a program for executing the method, includes a microcode unit for outputting control signals, for each of a plurality of instructions, required by the microprocessor for executing the instructions. The m... | 09/19/2006 |
| 7085913 | Hub/router for communication between cores using cartesian coordinates A method and structure for an integrated circuit is disclosed. The invention includes a plurality of logic cores, a plurality of local hubs connected to said logic cores, and a plurality of global hubs connected to said local hubs. The local hubs and the global hubs... | 08/01/2006 |
