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| Number | Title | Issue Date |
| 7532515 | Voltage reference generator using big flash cell A voltage reference generator includes multiple closed loop voltage references. Each of the closed loop voltage references uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The voltage reference generator includes s... | 05/12/2009 |
| 7519344 | Bandpass amplifier, method, and system An amplifier has a band pass response. The band pass response may be set by setting corner frequencies of low pass filters. ... | 04/14/2009 |
| 7492829 | Closed loop feedback in MIMO systems Feedback bandwidth may be reduced in a closed loop MIMO system by factoring non essential information out of a beamforming matrix. ... | 02/17/2009 |
| 7492222 | Compound automatic gain control A compound automatic gain control (AGC) circuit includes multiple AGC stages coupled with signal input nodes and signal output nodes in parallel. Each of the AGC stages has separate, individually controllable, control inputs. During gain back off, the AGC stages are... | 02/17/2009 |
| 7463093 | Variable gain amplifier A variable gain amplifier includes multiple gain stages. Each gain stage includes a gain transistor and a cascode transistor to form a cascode amplifier, and a current diversion transistor to divert current away from a cascode transistor to reduce gain in the stage.... | 12/09/2008 |
| 7456667 | Electrical signal duty cycle modification The duty cycle of a signal is modified by passing the signal through a plurality of inverting stages. The inverting stages each have bias circuitry to influence the input switching threshold of inverters. Multiple duty cycle modification circuits produce non-overlap... | 11/25/2008 |
| 7457393 | Clock recovery apparatus, method, and system A global clock recovery circuit and port circuit determine and combine static phase adjustment information and dynamic phase adjustment information for multiple data signals. Static phase adjustment information is determined for each of the multiple data signals, an... | 11/25/2008 |
| 7449919 | Driver circuit bias control A bias circuit includes multiple output legs. During a transition from a low power state to an operational state, multiple output legs are turned on to provide a bias voltage. After a suitable period, at least one of the multiple output legs is turned off. ... | 11/11/2008 |
| 7439804 | Amplifier with level shifting feedback network An amplifier circuit includes a low noise first stage and a wide dynamic range second stage. A feedback network coupled between the output of the second stage and the input of the first stage provides DC level shifting of the common mode input voltage. The common mo... | 10/21/2008 |
| 7424698 | Allocation of combined or separate data and control planes A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication. ... | 09/09/2008 |
| 7414478 | Integrated parallel power amplifier A parallel power amplifier includes a carrier amplifier and peak amplifier coupled to receive signals from a quadrature hybrid made up of slab inductors in an integrated circuit. The slab inductors may be on different layers in the integrated circuit and may have si... | 08/19/2008 |
| 7412221 | Crosstalk reduction method, apparatus, and system A data driver drives a data signal on a channel, and a current mode driver drives a varying current on the channel to reduce crosstalk. ... | 08/12/2008 |
| 7401246 | Nibble de-skew method, apparatus, and system De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits. ... | 07/15/2008 |
| 7393604 | Hybrid power system and method A hybrid power system includes a fuel cell and a secondary power source. ... | 07/01/2008 |
| 7366245 | Calibration in MIMO systems Aggregate channel reciprocity in a wireless system is supported by calibrating transmitter/receiver pairs. ... | 04/29/2008 |
| 7362246 | High speed comparator offset correction An offset canceling buffer receives a reference voltage, and provides a modified reference voltage to a comparator. The modified reference voltage operates to cancel any comparator offset. The offset canceling buffer includes a digitally controllable current source ... | 04/22/2008 |
| 7362822 | Recursive reduction of channel state feedback Feedback bandwidth may be reduced in a closed loop MIMO system by Householder transformations and vector quantization using codebooks. ... | 04/22/2008 |
| 7363491 | Resource management in security enhanced processors A processor divides resources into secure resources and non-secure resources. Virtual-to-physical address translation page tables may be stored in either secure or non-secure memory. ... | 04/22/2008 |
| 7362837 | Method and apparatus for clock deskew A clock signal is deskewed relative to a data signal by sweeping a sampling point in time and sweeping an amplitude offset. Bit error measurements are made at each sampling point in time and compared. Bit error measurements may be made by comparing received data to ... | 04/22/2008 |
| 7352819 | Multiantenna communications apparatus, methods, and system A transmitter may transmit using OFDM-MIMO or OFDM-SDMA depending on channel characteristics. ... | 04/01/2008 |
| 7349495 | Soft bits normalization apparatus, method, and system A receiver estimates a channel parameter from a received signal. The channel parameter may a DC signal level, a carrier to interference ratio, a noise spectrum, or the like. The receiver performs channel equalization and produces estimated symbols. The estimated sym... | 03/25/2008 |
| 7339403 | Clock error detection circuits, methods, and systems Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are unequally discharged based on the error. A positive feedback mechanism... | 03/04/2008 |
| 7334158 | Power fault handling method, apparatus, and system A processor may receive multiple signals corresponding to potential power faults. A control register in the processor may specify actions to be taken for each of the potential power faults. ... | 02/19/2008 |
