Leffert Jay & Polglaze, P.A. - US Patent Attorneys and Agents

Attorney: Leffert Jay & Polglaze, P.A.

Number of patents: 917
Last date: May 22, 2012

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Number	Title	Issue Date
8184489	Level shifting circuit A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the s...	05/22/2012
8184481	Memory devices and methods of their operation including selective compaction verify operations Memory devices and methods of their operation, where following an erasure of a string of memory cells, a selective compaction verify operation is performed on one or more, but less than all, of the memory cells of the string, and, if the selective compaction verify ...	05/22/2012
8183625	NROM flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the ga...	05/22/2012
8179725	Programming rate identification and control in a solid state memory Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory...	05/15/2012
8179724	Sensing for memory read and program verify operations in a non-volatile memory device Methods for sensing in a memory device and a memory device are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cel...	05/15/2012
8174897	Programming in a memory device Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses wher...	05/08/2012
8174893	Independent well bias management in a memory device Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one s...	05/08/2012
8174887	Adjusting for charge loss in a memory Memory and methods of operating a memory adjusting an output voltage of an analog storage device, such as a data cache capacitor holding a voltage level representative of data, in response to an estimated charge loss are useful for compensating for the effects of ch...	05/08/2012
8174081	Fully depleted silicon-on-insulator CMOS logic A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without t...	05/08/2012
8174061	Floating-gate structure with dielectric component Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate. The conductive portion includes a continuous component providing bulk conductivity to ...	05/08/2012
8171203	Faster write operations to nonvolatile memory using FSInfo sector manipulation An embodiment of the present invention includes a digital equipment system having a host for sending write commands to write files having sector information and having a controller device responsive to the commands for writing and updating FSInfo sector information....	05/01/2012
8171181	Memory module with configurable input/output ports A memory module has one or more memory devices, a controller in communication with the one or more memory devices, and a plurality of input/output ports. The controller is configured to configure each input/output port as an input, an output, or a bidirectional inpu...	05/01/2012
8169830	Sensing for all bit line architecture in a memory device Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the...	05/01/2012
8169808	NAND flash content addressable memory NAND architecture non-volatile content addressable (CAM) memory devices and methods are described that allows for high density, low cost CAM devices. In addition, the NAND architecture non-volatile CAM memory operates with reduced power consumption characteristics f...	05/01/2012
8166488	Methods of directly accessing a mass storage data device Methods of directly accessing a mass storage data device without communicating through an operating system layer are useful in recovering information previously stored in the mass storage device. ...	04/24/2012
8163610	Fabrication of finned memory arrays Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality fins is formed, the fins are isotropically etched to reduce a width of the fins and to round an upper sur...	04/24/2012
8161229	Flash memory architecture with separate storage of overhead and user data A memory device has a plurality of dedicated data blocks for storing only user data and a plurality of dedicated overhead blocks for storing only overhead data. Current overhead segments of a dedicated overhead block can be consolidated and moved to a new dedicated ...	04/17/2012
8159874	Cell operation monitoring Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of indiv...	04/17/2012
8151041	Removable storage device Methods and removable storage devices are provided. Some such removable storage devices may include a file specifying a name of a program to be executed automatically by a host, may include settings for a secure storage area, where the settings are user-configurable...	04/03/2012
8151040	Version based non-volatile memory translation layer A non-volatile memory and erase block/data block/sector/cluster update and address translation scheme utilizing a version number is detailed that enhances data updating and helps reduce program disturb of the memory cells of the non-volatile memory device. The vario...	04/03/2012
8144516	Dynamic pass voltage for sense operation in a memory device Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is adjacent to a selected memory cell for programming. If the adjacent memory cell is not programmed, the pass vol...	03/27/2012
8141443	Probe sensor shaft bearing adaptor assembly with conduit attachment A probe adaptor assembly includes a probe opening into which a probe can be inserted. The probe is held in place by a compression fitting such that the probe depth, with respect to a longitudinal axis of the assembly, can be adjusted prior to the compression fitting...	03/27/2012
8139421	Erase degradation reduction in non-volatile memory Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, ...	03/20/2012
8139419	Programming methods and memories Methods of programming memory cells, and memories incorporating such methods, are disclosed. In at least one embodiment, programming is accomplished by applying a set of incrementing program pulses to program a selected cell to a first target threshold voltage, and ...	03/20/2012
8135939	Robust index storage for non-volatile memory A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system w...	03/13/2012
8135925	Methods of operating a memory system Methods of operating a memory system are useful in facilitating access to data. Where repetitive data patterns are detected among portions of received data, and an indication is provided, a portion of the data may be stored and/or subsequently retrieved without havi...	03/13/2012
8134872	Apparatus and methods for programming multilevel-cell NAND memory devices Methods and apparatus are provided. A first data value is read from a first memory cell and is stored. An attempt is made to add a second data value to the first memory cell. If the attempt to add the second data value to the first memory cell is unsuccessful, the f...	03/13/2012
8134868	Memory device biasing method and apparatus Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example, alternating data lines are sensed while adjacent data lines are coupled to a c...	03/13/2012
8129243	Methods of forming non-volatile memory having tunnel insulator of increasing conduction band offset Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, ...	03/06/2012
8127091	Programming memory cells with additional data for increased threshold voltage resolution Methods for data transfer and/or programming a memory device, memory devices and memory systems are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appe...	02/28/2012
8125836	Verifying an erase threshold in a memory device In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, th...	02/28/2012
8125831	Sensing against a reference cell Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals representative of data values of two or more bits of information. Programming of such memory devices can include pr...	02/28/2012
8124491	Container capacitor structure and method of formation thereof Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proxi...	02/28/2012
8122321	Methods of data handling Methods of data handling include receiving data having a previously-generated error correction code and generating one or more error correction codes for the data, with each error correction code corresponding to the data having one or more particular bits of the da...	02/21/2012
8117375	Memory device program window adjustment In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory...	02/14/2012
8116143	Method of erasing memory cell An embodiment of a method of erasing a target memory cell includes grounding a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed...	02/14/2012
8116138	Memory device distributed controller system A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave con...	02/14/2012
8115477	Shaft speed sensor with analog output A 2-wire, loop-powered shaft rotational speed sensor device that outputs a 4-20 mA current in response to the shaft rotational speed. The device is comprised of a sensor (e.g., magnetic, optical) that senses an output from a sensor disk (e.g., magnetic, optical) and...	02/14/2012
8114737	Methods of forming memory cells on pillars and memories with memory cells on pillars Methods of fabricating memory are disclosed. For example, a method includes fabricating rows of memory cells on pillars separated by isolation regions therebetween. Each pillar has a pair of memory cells, each on an opposite side thereof. The method also includes fa...	02/14/2012
8112573	Non-volatile memory with erase block state indication in a subset of sectors of erase block An improved Flash memory device with a distributed erase block management (EBM) scheme is detailed that enhances operation and helps minimize write fatigue of the floating gate memory cells of the Flash memory device. The Flash memory device of the invention combine...	02/07/2012

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Attorney: Leffert Jay & Polglaze, P.A.