Leffert Jay & Polglaze, P.A. - US Patent Attorneys and Agents

Attorney: Leffert Jay & Polglaze, P.A.

Number of patents: 1028
Last date: May 21, 2013

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Number	Title	Issue Date
8446787	Replacing defective memory blocks in response to external addresses Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective memory block of a sequence of memory blocks of the memory device in place of a defective memo...	05/21/2013
8446784	Level shifting circuit A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the s...	05/21/2013
8446767	Memories and their formation Memories and their formation are disclosed. One such memory has first and second memory cells at a first vertical level of the memory, first and second memory cells at a second vertical level of the memory, a first data line is selectively coupled to the first memor...	05/21/2013
8441873	Memory devices and methods of operating memory Methods and apparatus for synchronizing a delay locked loop, such as delay locked loops used with NAND memories are disclosed. In at least one embodiment, one or both of a clock and the delay locked loop are stopped for energy savings. A synchronization start signal...	05/14/2013
8441860	NAND step up voltage switching method Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment ...	05/14/2013
8441858	Apparatus having a string of memory cells Apparatus having a string of memory cells are useful in semiconductor memory. Some apparatus have circuitry configured to program memory cells of the string in a particular sequence. Some apparatus have circuitry configured to program a threshold voltage of a select...	05/14/2013
8441855	Strings of memory cells having string select gates, memory devices incorporating such strings, and methods of accessing and forming the same Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For exampl...	05/14/2013
8441056	NROM memory cell, memory array, related devices and methods An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing...	05/14/2013
8437198	Method for discharging a voltage from a capacitance in a memory device In discharging a voltage from a circuit capacitance, a supply voltage to a memory device is monitored. The capacitance is discharged through a discharge circuit from a relatively high voltage to a relatively low voltage when the supply voltage decreases below a trip...	05/07/2013
8428736	Muscle stimulator and control methods therefor Apparatus and methods for muscle stimulation and control of muscle stimulators are disclosed. In at least one embodiment, an electrical muscle stimulator includes a belt having a plurality of stimulator pads, a pulse width modulator controlled by a feedback loop, th...	04/23/2013
8422312	Systems and methods for erasing a memory Methods of erasing a memory, methods of operating a memory, memory devices, and systems. In one such method, an erase block is erased to an intermediate erase voltage before it is erased to a final erase voltage, such as to tighten an erase distribution. Faster eras...	04/16/2013
8422297	Multi level inhibit scheme Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions having boosted channel bias levels are formed across multiple memory cells and are created in part and ma...	04/16/2013
8416628	Local sensing in a memory device Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by ...	04/09/2013
8415715	Discrete trap non-volatile multi-functional memory device A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate ...	04/09/2013
8411511	Reading data from memory cells including storing charges to analog storage devices Methods of reading data from memory cells. Such methods include subjecting an analog storage device to a voltage level indicative of a threshold voltage of a memory cell to store a charge to the analog storage device, and generating an analog voltage from the stored...	04/02/2013
8407254	Systems for receiving and forming marketplaces for working on digital information blocks A remote access medical image exchange system utilizes a decentralized, i.e., self-organizing, distribution system combined with bid queues to establish a market place which allows for continuously negotiated prices with control (over who reads the images, when they...	03/26/2013
8406050	Current sensing for flash A current sensing data read/verify process and sense amplifier is described that senses memory cells of a non-volatile memory array utilizing a current sensing process that places a current source to provide current to the bit line. The voltage level of the bit line...	03/26/2013
8405444	Voltage switching in a memory device Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series...	03/26/2013
8404536	Method for fabricating stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich s...	03/26/2013
8400826	Coarse and fine programming in a solid state memory Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory...	03/19/2013
8399952	Integrated circuit devices having a strontium ruthenium oxide interface Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing...	03/19/2013
8399347	Integrated circuits and methods of forming conductive lines and conductive pads therefor Integrated circuits and methods for forming conductive lines and conductive pads of integrated circuits are disclosed. One such integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a ...	03/19/2013
8397019	Memory for accessing multiple sectors of information substantially concurrently A memory storage system of an embodiment includes a non-volatile memory unit and memory control circuitry coupled to the memory unit. The memory control circuitry is configured to access multiple sectors of information substantially concurrently. ...	03/12/2013
8395941	Multi-semiconductor material vertical memory strings, strings of memory cells having individually biasable channel regions, memory arrays incorporating such strings, and methods of accessing and forming the same Multi-semiconductor vertical memory strings, strings of memory cells having individually biasable channel regions, arrays incorporating such strings and methods for forming and accessing such strings are provided. For example non-volatile memory devices are disclose...	03/12/2013
8395939	Compensation of back pattern effect in a memory device In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals ...	03/12/2013
8395140	Cross-point memory utilizing Ru/Si diode Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface on the silicon material of ruthenium or ...	03/12/2013
8391080	Erase voltage reduction in a non-volatile memory device In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase ...	03/05/2013
8386724	Methods and apparatus for designating or using data status indicators Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data va...	02/26/2013
8386695	Methods and apparatus for writing data to non-volatile memory Methods and apparatus for writing data to non-volatile memory include maintaining one or more lists of obsolete blocks of the non-volatile memory and limiting the lists to a predetermined value. If a write operation would result in a list exceeding its predetermined...	02/26/2013
8385123	Programming to mitigate memory cell performance differences Methods for programming and memory devices are disclosed. In one such method for programming, a first programming voltage applied to control gates of a group of memory cells generates a maximum threshold voltage of the group of memory cell threshold voltages. A volt...	02/26/2013
8385121	Memory adapted to program a number of bits to a memory cell and read a different number of bits from the memory cell A memory has a memory array with a memory cell. The memory is adapted to program a first number of bits into the memory cell. The memory is adapted to sense a second number of bits, different from the first number of bits, from the memory cell. ...	02/26/2013
8385118	Multi-pass programming in a memory device A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells t...	02/26/2013
8381076	Variable sector-count ECC Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by increasing the data area of user data being covered by the ECC code. This averages any possible bit errors over a ...	02/19/2013
8379461	Program and sense operations in a non-volatile memory device Methods for programming and sensing in a memory device, a data cache, and a memory device are disclosed. In one such method, all of the bit lines of a memory block are programmed or sensed during the same program or sense operation by alternately multiplexing the od...	02/19/2013
8379446	Memory controller self-calibration for removing systemic influence Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change...	02/19/2013
8378412	Memory arrays where a distance between adjacent memory cells at one end of a substantially vertical portion is greater than a distance between adjacent memory cells at an opposing end of the substantially vertical portion and formation thereof Memory arrays and their formation are disclosed. One such memory array has a string of series-coupled memory cells with a substantially vertical portion. A distance between adjacent memory cells at one end of the substantially vertical portion is greater than a dist...	02/19/2013
8375179	Method for reading a multilevel cell in a non-volatile memory device A non-volatile memory device has a memory array comprising a plurality of memory cells. The array can operate in either a multilevel cell or single level cell mode and each cell has a lower page and an upper page of data. The memory device has a data latch for stori...	02/12/2013
8375157	Cluster based non-volatile memory translation layer An improved non-volatile memory and logical block to physical block address translation method utilizing a cluster based addressing scheme is detailed. The translation of logical blocks/sectors to the physical blocks/sectors is necessary for a non-volatile memory to...	02/12/2013
8374037	Method for programming a semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintai...	02/12/2013
8374028	Sense operation in a memory device Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sens...	02/12/2013

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Attorney: Leffert Jay & Polglaze, P.A.