A simulation environment for the sport of boxing utilizing a robotic machine interface system which carries a person.
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6963033 | Ball grid array attaching means having improved reliability and method of manufacturing same An array of solder structures comprising a plurality of radially-curved exterior surfaces, each one enclosing a predetermined-sized cavity that can be used for flexibly joining together at predetermined conductive contact points two planar elements having dissimilar... | 11/08/2005 |
| 6912114 | High-capacitance capacitor having multi-layered vertical structure A high-capacitance capacitor having a multi-layered vertical structure for use in an RF circuit is disclosed. The capacitor includes an upper electrode, a lower electrode, and a dielectric layer interposed between the two electrodes. A plurality of electrodes is for... | 06/28/2005 |
| 6893501 | Method for manufacturing a semiconductor device having a capping layer covering a capacitor of the semiconductor device A method for manufacturing a capping layer covering a capacitor of a semiconductor memory device, preferably a metal-insulator-metal (MIM) capacitor, wherein the method includes forming a capacitor having a lower electrode, a dielectric layer and an upper electrode ... | 05/17/2005 |
| 6885138 | Ferroelectric emitter A ferroelectric multi-layered emitter used in a semiconductor lithography process includes a lower electrode, a ferroelectric layer, having a top surface with two end portions, which overlies the lower electrode, an insertion electrode formed on a region excluding t... | 04/26/2005 |
| 6882215 | Substrate bias generator in semiconductor memory device A substrate bias generator which makes device characteristics stable by supplying a predetermined negative voltage to a substrate and minimally reduces current consumption during a self refresh mode. The substrate bias generator comprises a substrate voltage level d... | 04/19/2005 |
| 6866963 | Cathode active material and lithium battery employing the same A cathode active material and a lithium secondary battery employing the same are provided. In the cathode active material includes cyclic bis (2,5-bis-dithio-1,4-dimethoxybenzene) represented by formula 1: ... | 03/15/2005 |
| 6865067 | Structure of radio frequency variable capacitor and method of manufacturing the same In a structure of a radio frequency (RF) variable capacitor having a variable range of capacitance between a first minimum value and a first maximum value, and a method of manufacturing the structure, the structure includes a first capacitor, which has a variable ra... | 03/08/2005 |
| 6861686 | Structure of a CMOS image sensor and method for fabricating the same An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positione... | 03/01/2005 |
| 6858326 | Blue electroluminescent polymer and organic electroluminescence device using the same A blue electroluminescent polymer comprising diphenylanthracene units in a main chain of polymer and an organic electroluminescence device using the blue electroluminescent polymer, to provide improved luminescent properties. ... | 02/22/2005 |
| 6858269 | Photo-alignment materials for liquid crystal alignment film A photo-alignment material useful in liquid crystal alignment films comprises a maleimide-based repeating unit, or a maleimide-based repeating unit and at least one additional repeating unit. The photo-alignment materials of the invention may be used in liquid cryst... | 02/22/2005 |
| 6855603 | Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon n... | 02/15/2005 |
| 6855591 | Nonvolatile memory device having STI structure and method of fabricating the same A nonvolatile memory device and a method of forming the nonvolatile memory device having a shallow trench isolation structure and having a device isolation layer having a protruding portion above a substrate surface includes forming a gate oxide, a lower conductive ... | 02/15/2005 |
| 6855590 | Method of manufacturing the semiconductor device intended to prevent a leakage current from occuring due to a gate induced drain leakage effect A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the ... | 02/15/2005 |
| 6853599 | Magnetic memory device implementing read operation tolerant to bitline clamp voltage (VREF) A magnetic memory device includes a memory cell array block and a reference memory cell array block having a plurality of magnetic memory cells arranged, respectively, at intersections of wordlines, digit lines, and bitlines, and reference wordlines, the digit lines... | 02/08/2005 |
| 6849889 | Semiconductor device having storage node contact plug of DRAM (dynamic random access memory) A method for forming a storage node contact plug of a dynamic random access memory includes forming insulating layers on an overall surface of a semiconductor substrate having a plurality of buried contact plugs, etching the insulating layers down to a top surface o... | 02/01/2005 |
| 6849520 | Method and device for forming an STI type isolation in a semiconductor device A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner side... | 02/01/2005 |
| 6842475 | Apparatus for acquisition of asynchronous wideband DS/CDMA signal An apparatus for acquisition of an asynchronous wideband direct-sequence/code division multiple access signal, which acquires a long code from a direct-sequence/code division multiple access control channel signal, in which a common short code, and the long code are... | 01/11/2005 |
| 6841851 | Semiconductor device having a high density plasma oxide layer A semiconductor device and a method for manufacturing the same, wherein a gate electrode structure is formed on a surface of a semiconductor substrate. Next, a gate poly oxide (GPOX) layer is deposited on a surface of the gate electrode structure and on the semicond... | 01/11/2005 |
| 6841268 | Blue electroluminescent polymer and organic electroluminescence device using the same A blue electroluminescent polymer comprising biphenyl units in a main chain of polyarylene, and an organic electroluminescence device using the blue electroluminescent polymer to provide improved luminescent properties. ... | 01/11/2005 |
| 6840846 | Polishing station of a chemical mechanical polishing apparatus An apparatus for polishing a wafer includes a polishing station having a platen on which a polishing pad is installed, a polishing head having a membrane that contacts a surface of the wafer, the membrane securing the wafer and pressuring the wafer against the polis... | 01/11/2005 |
| 6840457 | Wet-pipe sprinkler system, method of supplying water and dealing with water leak in the sprinkler system A wet-pipe sprinkler system, method of supplying water to the system, and method of dealing with a leakage of the system are provided, wherein the wet-pipe sprinkler system includes a sprinkler head; a plurality of interconnected pipes for supplying water to the spr... | 01/11/2005 |
| 6839786 | Information processing system with memory modules of a serial bus architecture An information processing system for controlling clock skew preferably includes a first and a second memory module, each of which has at last one semiconductor integrated circuit and is controlled by a chipset which can selectively control the time delay of an indiv... | 01/04/2005 |
| 6838727 | Memory device using a transistor and one resistant element for storage A memory device having one transistor and one resistant element as a storing means and a method for driving the memory device, includes an NPN-type transistor formed on a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate to... | 01/04/2005 |
| 6838330 | Method of forming a contact hole of a semiconductor device A method of forming a contact hole of a semiconductor device that is able to prevent excessive etching of an interlayer dielectric pattern includes forming a gate pattern including a first insulation layer pattern, a conductive layer pattern, a capping insulation la... | 01/04/2005 |
| 6838223 | Compositions for anti-reflective light absorbing layer and method for forming patterns in semiconductor device using the same A composition for an anti-reflective layer capable of simultaneously being developed together with a photoresist layer after exposure of the photoresist layer in a photolithography process and a method for forming patterns in a semiconductor device using the composi... | 01/04/2005 |
| 6837619 | Furnace temperature detector A furnace temperature detector includes a spike thermocouple attached to a heating chamber; an overheat thermocouple attached to the heating chamber; an inner thermocouple installed inside a reaction tube; a temperature controller connected to the spike thermocouple... | 01/04/2005 |
| 6835996 | Method and device for forming an STI type isolation in a semiconductor device A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner side... | 12/28/2004 |
| 6835919 | Inductively coupled plasma system An inductively coupled plasma apparatus is provided, wherein the inductively coupled plasma apparatus includes a process chamber having a wafer susceptor on which a substrate is installed, a top plasma source chamber which is installed on the process chamber, a reac... | 12/28/2004 |
| 6835594 | Metal wiring method for an undercut A metal wiring method for an undercut in a MEMS packaging process includes disposing a MEMS element on a silicon substrate, welding a glass wafer to an upper portion of the silicon substrate having the MEMS element disposed thereon, the glass wafer having a hole for... | 12/28/2004 |
| 6835529 | Polymer having butadiene sulfone repeating unit and resist composition comprising the same A polymer having a repeating unit comprising a copolymer of butadiene sulfone and maleic anhydride, and a chemically amplified resist composition comprising the polymer. The resist composition includes a photosensitive polymer having a first repeating unit comprisin... | 12/28/2004 |
| 6835492 | Method for forming lithium metal anode protective layer for lithium battery and lithium battery having such protective layer A method for forming a lithium anode protective layer comprises activating the surface of the lithium metal anode and forming a LiF protective layer on the activated surface of the lithium metal anode. ... | 12/28/2004 |
| 6833621 | Metal gasket for a semiconductor fabrication chamber A metal gasket for a semiconductor fabrication chamber capable of preventing base plate metal contamination in the chamber, wherein the metal gasket includes a diffusion barrier layer interposed between a base plate and an anti-corrosive coating layer, and wherein t... | 12/21/2004 |
| 6833567 | Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon n... | 12/21/2004 |
| 6833310 | Semiconductor device having thin film formed by atomic layer deposition and method for fabricating the same A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate... | 12/21/2004 |
| 6833050 | Apparatus for manufacturing semiconductor device An apparatus for improving the density and uniformity of plasma in the manufacture of a semiconductor device features a plasma chamber having a complex geometry that causes plasma density to be increased at the periphery or edge of a semiconductor wafer being proces... | 12/21/2004 |
| 6829189 | Semiconductor memory device and bit line sensing method thereof In a semiconductor memory device, a circuit for controlling a voltage level applied to a bit line isolation circuit preferably includes a memory cell connected between a cell bit line pair and a word line; a bit line pre-charge circuit; a sense amplifier bit line pr... | 12/07/2004 |
| 6828617 | Method for fabricating a capacitor of a semiconductor device and a capacitor made thereby A method for fabricating a capacitor of a semiconductor device, and a capacitor made in accordance with the method, wherein the method includes forming a plate electrode polysilicon layer on a semiconductor substrate having a cell array region and a core/peripheral ... | 12/07/2004 |
| 6828254 | Plasma enhanced chemical vapor deposition apparatus and method for forming nitride layer using the same A plasma enhanced chemical vapor deposition apparatus and a method of forming a nitride layer using the same, wherein the plasma enhanced CVD apparatus includes a process chamber including an upper chamber with a dome shape, a lower chamber, and an insulator therebe... | 12/07/2004 |
| 6826743 | Method for automatically correcting overlay alignment of a semiconductor wafer A semiconductor wafer overlay correction method for an exposure process in a semiconductor fabricating stepper incorporates variations in equipment characteristics with time. The wafer overlay correction method includes measuring an overlay error correction value of... | 11/30/2004 |
| 6825121 | Method of manufacturing a capacitor of a semiconductor device A method of manufacturing a capacitor having increased capacitance using a single photo-lithographic step to form two holes of different sizes in the insulating layers, wherein a first insulating layer, an etching stop layer, and a second insulating layer are sequen... | 11/30/2004 |