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| Number | Title | Issue Date |
| 8139311 | Apparatus, method and program for controlling writing of data by tape recording apparatus A technique for improving the performance of head alignment during reading of data from and writing data to a tape medium. An apparatus controls writing of data by a tape drive that drives a tape medium in both forward and reverse directions to record data. The appa... | 03/20/2012 |
| 8132131 | Design structure including failing address register and compare logic for multi-pass repair of memory arrays Disclosed is design structure including an integrated circuit having a system for moving a failing address into a new FAR by utilizing the functional compare circuitry during BIST of redundant memory elements. Disclosed is an any-for-any scheme that eliminates the t... | 03/06/2012 |
| 8090976 | Error correction for digital systems An interface system is provided between a source component (210) and a destination component (220) having multiple parallel lines for transmitting data or parity bits (231-234, 251-253) and one or more spare lines (241-24... | 01/03/2012 |
| 8046566 | Method to reduce power consumption of a register file with multi SMT support A method for reducing the power consumption of a register file of a microprocessor supporting simultaneous multithreading (SMT) is disclosed. Mapping logic and associated table entries monitor a total number of processing threads currently executing in the processor... | 10/25/2011 |
| 8019276 | Audio transmission method and system An audio transmission method and system. The method includes detecting by a computing system, a wireless device belonging to a user. The computing system enables a connection between the wireless device and the computing system. The computing system receives from th... | 09/13/2011 |
| 8010860 | Method and architecture to prevent corrupt data propagation from a PCI express retry buffer A PCI Express compliant method and apparatus for preventing corrupt data being transmitted from a retry buffer of a transmitting component to a receiving component over a PCI Express compliant link. The method including storing parity or electronic error correction ... | 08/30/2011 |
| 7996747 | Forward error correction encoding for multiple link transmission compatible with 64B/66B scrambling A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before a... | 08/09/2011 |
| 7996738 | Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subd... | 08/09/2011 |
| 7985643 | Semiconductor transistors with contact holes close to gates A semiconductor structure. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically... | 07/26/2011 |
| 7971176 | Method for testing integrated circuits A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the ne... | 06/28/2011 |
| 7961932 | Method and apparatus for manufacturing diamond shaped chips In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of c... | 06/14/2011 |
| 7954028 | Structure for redundancy programming of a memory device A design structure for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, circuits for implementing a method wherein it is assumed that all fails are r... | 05/31/2011 |
| 7949853 | Two dimensional addressing of a matrix-vector register array A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column h... | 05/24/2011 |
| 7526743 | Method for routing data paths in a semiconductor chip with a plurality of layers The present invention relates to a method for routing data paths in a semiconductor chip with a plurality of layers. The inventive method comprises the steps of wiring a launching clock path and a receiving clock path on one or more layers according to at least one ... | 04/28/2009 |
| 7526698 | Error detection and correction in semiconductor structures A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and secon... | 04/28/2009 |
| 7515666 | Method for dynamically changing the frequency of clock signals A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second ... | 04/07/2009 |
| 7490280 | Microcontroller for logic built-in self test (LBIST) Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware descrip... | 02/10/2009 |
| 7463083 | Noise reduction in digital systems when the noise is caused by simultaneously clocking data registers A digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of ... | 12/09/2008 |
| 7459958 | Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first... | 12/02/2008 |
| 7457895 | Dynamic memory allocation between inbound and outbound buffers in a protocol handler An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer... | 11/25/2008 |
| 7454642 | Method and architecture for power management of an electronic device A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional cir... | 11/18/2008 |
| 7453296 | Delay locked loop having charge pump gain independent of operating frequency A delay locked loop (DLL) having a charge pump gain independent of the operating frequency of the DLL. A method for providing a constant gain for a charge pump component of a delay locked loop (DLL) is disclosed, and includes: providing a switched capacitor stage re... | 11/18/2008 |
| 7453740 | Method and apparatus for initializing reference cells of a toggle switched MRAM device A method of determining an initial state of a reference cell in a fabricated memory array includes performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells, ... | 11/18/2008 |
| 7408800 | Apparatus and method for improved SRAM device performance through double gate topology A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the stor... | 08/05/2008 |
| 7406571 | Memory system and method for controlling the same, and method for maintaining data coherency A memory system including a bus 10, 11, a memory 17, a memory controller 16, a first device 13 having a cache, and a second device 15, all connected to the bus, wherein the memory controller includes a buffer 20 for temporar... | 07/29/2008 |
| 7404125 | Compilable memory structure and test methodology for both ASIC and foundry test environments A memory structure configured for supporting multiple test methodologies includes a first plurality of multiplexers configured for selectively coupling at least one data input path and at least one address path between an external customer connection and a correspon... | 07/22/2008 |
| 7404114 | System and method for balancing delay of signal communication paths through well voltage adjustment A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A r... | 07/22/2008 |
| 7397718 | Determining relative amount of usage of data retaining device based on potential of charge storing device A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the cha... | 07/08/2008 |
| 7397641 | Apparatus and method for improved triggering and oscillation suppression of ESD clamping devices An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger de... | 07/08/2008 |
| 7397692 | High performance single event upset hardened SRAM cell An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET inter... | 07/08/2008 |
| 7386771 | Repair of memory hard failures during normal operation, using ECC and a hard fail identifier circuit A memory sub-system and a method for operating the same. The memory sub-system includes (a) a main memory, (b) an ECC circuit, (c) a hard fail identifier circuit, (d) a repair circuit, (e) a redundant memory, and (f) a threshold setting circuit. The ECC circuit is c... | 06/10/2008 |
| 7375339 | Monitoring ionizing radiation in silicon-on insulator integrated circuits A method, device and system for monitoring ionizing radiation. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon subst... | 05/20/2008 |
| 7362184 | Frequency divider monitor of phase lock loop A circuit and method for monitoring a frequency divider. The circuit including a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedbac... | 04/22/2008 |
| 7355486 | Current controlled oscillation device and method having wide frequency range A current controlled, phase locked loop device includes a phase detector configured to compare a reference frequency to an output frequency of a current controlled oscillator (ICO), a charge pump coupled to the phase detector and a low pass filter coupled to the cha... | 04/08/2008 |
| 7333379 | Balanced sense amplifier circuits with adjustable transistor body bias Structures of balanced sense amplifier circuits and methods for operating the same. The structure comprises a reading circuit, which includes a first transistor and a second transistor. The first and second transistors comprise (i) a first transistor body and a seco... | 02/19/2008 |
| 7331021 | Fast/slow state machine latch A fast/slow state machine latch is provided that generates fast and slow select signals for a single toggle, low power multiplexer circuit. In accordance with an embodiment of the present invention, the fast/slow state machine latch includes a first latch with a del... | 02/12/2008 |
| 7321617 | Data communication system with self-test feature A data communication system includes circuitry to assure components respond to variations in the time length of the valid data window or “eye” of the high speed data communication signal. A self-test portion of the system periodically injects the effects of phas... | 01/22/2008 |
| 7317348 | Noise reduction in digital systems A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. Th... | 01/08/2008 |
| 7313045 | Dynamic semiconductor storage device To achieve, by a simple circuit configuration, a DRAM that permits refresh current to be effectively reduced by selectively setting refresh cycles. A memory cell array is divided into 64 subarrays, and each subarray is further divided into 8 blocks. A refresh cycle ... | 12/25/2007 |
| 7313738 | System and method for system-on-chip interconnect verification A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip componen... | 12/25/2007 |
