LeStrange, Esq.; Michael J. - US Patent Attorneys and Agents

Attorney: LeStrange, Esq.; Michael J.

Number of patents: 36
Last date: March 13, 2012

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Number	Title	Issue Date
8136010	Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs A CRC redundancy calculation circuit and a design structure including the circuit embodied in a machine readable medium are presented. The CRC redundancy calculation circuit is pipelined to run at high frequencies and configured to operate on an arbitrary multiple o...	03/13/2012
8126041	Circuit and method for on-chip jitter measurement Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line ...	02/28/2012
8122395	On chip timing adjustment in multi-channel fast data transfer A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signal...	02/21/2012
8087823	Method for monitoring thermal control A structure has a heat dissipating feature, an internal temperature measurement device, and a memory. The structure generates heat as power is supplied to the structure, and a threshold voltage of the internal temperature measurement device changes as the temperatur...	01/03/2012
8051359	System and method for optimizing iterative circuit for cyclic redundency check (CRC) calculation A system for generating CRC code words associated with data ranging up to w-bytes in width to be communicated over a communications channel includes a first plurality of serially coupled code-generation blocks each for generating a CRC value based on data input to e...	11/01/2011
8021950	Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation Disclosed are embodiments of a semiconductor wafer processing method that allow device regions to be selectively annealed following back end of the line (BEOL) metal wiring formation without degrading wiring layer reliability. In the embodiments, a semiconductor dev...	09/20/2011
8010813	Structure for system for extending the useful life of another system Disclosed is a design structure for an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includ...	08/30/2011
7996739	Avoiding race conditions at clock domain crossings in an edge based scan design A structure, system, and method block clock inputs to clock domains (using a computer). While the clock domain inputs are blocked, the structure, system, and method perform a first timing test only of signals that are transmitted within the clock domains (using the ...	08/09/2011
7966589	Structure for dynamic latch state saving device and protocol The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allo...	06/21/2011
7956671	Circuit structure and method for programming and re-programming a low power, multiple states, electronic fuse (e-fuse) In one embodiment of an e-fuse programming/re-programming circuit, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source i...	06/07/2011
7898285	Optimal local supply voltage determination circuit A test circuit that compares test results between two tests with different local supply voltages is provided. The output of each stage of the logic circuits is stored in a first register of each test circuit. Each test is performed with a critical test vector and a ...	03/01/2011
7890892	Balanced and bi-directional bit line paths for memory arrays with programmable memory cells Disclosed is a design structure of an improved large scale memory system and, more particularly, an improved memory system that incorporates an array of memory cells that are subjected to minimal location dependent power variations and that, optionally, allows for b...	02/15/2011
7886210	Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs A CRC redundancy calculation circuit is presented which is pipelined to run at high frequencies and configured to operate on an arbitrary multiple of the base granularity of the data packet. Additionally, the CRC redundancy calculation circuit provides the same mult...	02/08/2011
7882455	Circuit and method using distributed phase change elements for across-chip temperature profiling Disclosed is an across-chip temperature sensing circuit and an associated method that can be used to profile the across-chip temperature gradient. The embodiments incorporate a plurality of phase change elements distributed approximately evenly across the semiconduc...	02/01/2011
7869379	Method for monitoring channel eye characteristics in a high-speed SerDes data link A method is disclosed for tuning each channel of a high-speed SerDes cable link interface arranged in a configuration linking a local side physical layer to a remote side physical layer. The method includes initiating an operational state of high-speed SerDes cable ...	01/11/2011
7853848	System and method for signature-based systematic condition detection and analysis Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated b...	12/14/2010
7826288	Device threshold calibration through state dependent burn-in In a method for reducing and/or eliminating mismatch in one or more devices that require a balanced state (e.g., in cross-coupled transistors in each memory cell and/or sense amp in a memory array), the bias (i.e., the preferred state) of each of the devices is dete...	11/02/2010
7823107	Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least o...	10/26/2010
7791933	Optimized phase change write method A system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC), and a design structure including the IC embodied in a machine readable medium are disclosed. The system includes an array of phase change elements with a plurality...	09/07/2010
7757137	Method and apparatus for on-the-fly minimum power state transition The invention includes a novel scan chain structure for LSSD or GSD IC operation. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in sc...	07/13/2010
7715323	Method for monitoring BER in an infiniband environment A method is disclosed for tuning each channel of a high-speed SerDes cable link interface arranged in a configuration linking a local side physical layer to a remote side physical layer. The method includes initiating an operational state of high-speed SerDes cable ...	05/11/2010
7705626	Design structure to eliminate step response power supply perturbation A design structure for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header...	04/27/2010
7692944	3-dimensional integrated circuit architecture, structure and method for fabrication thereof An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently opt...	04/06/2010
7644327	System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented...	01/05/2010
7594140	Task based debugger (transaction-event-job-trigger) The embodiments of the invention provide an apparatus, method, etc. for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores...	09/22/2009
7511528	Device and method to eliminate step response power supply perturbation A system and method for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary heade...	03/31/2009
7478280	Test system for integrated circuits A test board includes a plurality of sockets for connection to a plurality of integrated circuit chips to be tested. A test control device on the board turns on at least one test engine for testing the plurality of chips simultaneously. A checking circuit verifies t...	01/13/2009
7458000	Automatic shutdown or throttling of a bist state machine using thermal feedback A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied. The thermal sensor device compares the current temperature val...	11/25/2008
7444564	Automatic bit fail mapping for embedded memories with clock multipliers A bit fail map circuit accurately generates a bit fail map of an embedded memory such as a DRAM by utilizing a high speed multiplied clock generated from a low-speed Automated Test Equipment (ATE) tester. The circuit communicates between the ATE tester, the embedded...	10/28/2008
7373567	System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented...	05/13/2008
7213196	Method and system for indexing a decoder A data driven clock recovery system comprising a viterbi detector for detecting data and tentatively deciding the closest approximation, and a circuit for retrieving the tentative decision in stages. Preferably, the clock recovery system further comprises a combinat...	05/01/2007
7191383	System and method for optimizing iterative circuit for cyclic redundancy check (CRC) calculation A system for generating CRC code words associated with data ranging up to w-bytes in width. The system is an iterative approach for providing a CRC calculation circuitry with the CRC calculation being subdivided into a blocks with selectable bus widths which blocks ...	03/13/2007
7170299	Electronic fuse blow mimic and methods for adjusting electronic fuse blow A system, method and program product for adjusting an environmental variable of a fuse blow of an electronic fuse are disclosed. A mimic NFET is coupled to a fuse blow source voltage line, a fuse blow gate voltage line, and a chip ground in the same manner as the el...	01/30/2007
7139950	Segmented scan chains with dynamic reconfigurations A method is disclosed of diagnosing defects in scan chains by statically and dynamically segmenting and reconfiguring the scan chains. A plurality of serially extending scan chains are partitioned into a plurality of serially arranged equal length segments such that...	11/21/2006
7085993	System and method for correcting timing signals in integrated circuits A system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device. The system includes a clock generator circuit for providing a clock signal used for tim...	08/01/2006
7057180	Detector for alpha particle or cosmic ray A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches ...	06/06/2006

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Attorney: LeStrange, Esq.; Michael J.