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| Number | Title | Issue Date |
| 8184501 | Systems and methods for stretching clock cycles in the internal clock signal of a memory array macro Systems and methods for stretching clock cycles of the internal clock signal of a memory array macro to allow more time for a data access in the macro than the period of an external clock signal. In one embodiment, a local clock buffer in the memory array macro rece... | 05/22/2012 |
| 8125177 | System and method for adding voltages of power modules in variable frequency drives Systems and methods for providing electrical power and to downhole oil production equipment such as electrical submersible pumps, wherein the outputs of multiple power modules are individually filtered before being added together to obtain a high voltage output that... | 02/28/2012 |
| 8122279 | Multiphase clocking systems with ring bus architecture Systems and methods for transferring data using a ring bus architecture in a system that implements multi-phase clocking. In one embodiment, the system is a multiprocessor having multiple processor cores coupled to the ring bus. The bus may be a bidirectional bus ha... | 02/21/2012 |
| 8112830 | Neck guard for use in a hair-washing sink A neck guard for a salon/barber industry sink, wherein the sink has an indentation in a lip of the sink to accommodate a person's neck. The neck guard includes a lower layer, a cushioning layer and a cover layer. The lower layer is flexible and incorporates fastener... | 02/14/2012 |
| 8092190 | Systems and methods for reducing pump downtime by determining rotation speed using a variable speed drive Systems and methods for using variable speed drives to restart downhole submersible pump motors. In one embodiment, a downhole pump is controlled using a variable speed drive that includes a control system configured to detect interruptions in the operation of the p... | 01/10/2012 |
| 8089319 | Wide range interpolative voltage controlled oscillator Systems and methods for increasing the frequency range of an output signal generated by a VCO, where one or more variable delay units are incorporated into an interpolative VCO to decrease the minimum frequency at which the VCO oscillates. In one embodiment, the VCO... | 01/03/2012 |
| 7994830 | Systems and methods for PLL linearity measurement, PLL output duty cycle measurement and duty cycle correction Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the fr... | 08/09/2011 |
| 7974605 | Personal communications processing system Systems and methods for processing personal communications wherein one embodiment comprises a communication processing system which has a data processing system that receives communications from a user. The data processing system authenticates the received communica... | 07/05/2011 |
| 7940544 | Memory system having multiple vias at junctions between traces An improvement to a memory system having a hierarchical bitline structure wherein traces that form global write lines are connected to each other using junctions that include multiple vias to reduce capacitance and increase yield. At least one of a pair of traces co... | 05/10/2011 |
| 7936490 | System and methods for shearless hologram acquisition Systems and methods for shearless digital hologram acquisition, including an apparatus incorporating an illumination source configured to produce a first beam of light, which is then split by a beamsplitter into a reference beam and an object illumination beam. The ... | 05/03/2011 |
| 7918626 | Systems and methods for pipe replacement Systems and methods for concurrently destroying old pipes and installing new pipes in their place. An exemplary embodiment is a pipe bursting and replacement tool that includes a body and first and second connectors. The body has a shape that generally tapers from a... | 04/05/2011 |
| 7913006 | Self-organized parallel processing system Systems and methods for improving the performance of a multimedia processor system by dynamically evaluating the current performance of the system and, if necessary, updating the configurations of the individual processors to improve the performance of the system. O... | 03/22/2011 |
| 7886257 | Methods for hierarchical noise analysis Systems and methods for hierarchical noise analysis of digital circuits, wherein analysis of a cell is based on the configuration of the cell itself and also the upstream circuit components that are connected to the inputs of the cell. One embodiment comprises a met... | 02/08/2011 |
| 7854254 | Systems and methods for making seals in heat exchangers Systems and methods for improving heat exchangers by implementing self-energizing seals. In one embodiment, a U-tube heat exchanger includes a shell enclosure, a tube sheet, a closure and a set of tubes welded to the tube sheet. The tube sheet separates first and se... | 12/21/2010 |
| 7834643 | Systems and methods for reducing distortion in a power source using an active harmonics filter Systems and methods for reducing harmonic distortion in a power system resulting from non-linear loading on the power system. The power at an interface with a power source is measured, and then distortion in the waveforms of the supplied power is identified. Cancell... | 11/16/2010 |
| 7825790 | Emergency vehicle light bar with message display A lighting subsystem and a light bar structure upon which the lighting subsystem is mounted. The lighting subsystem has a display that incorporates both warning signal lights and a programmable message display and is configured to enable the positioning of the light... | 11/02/2010 |
| 7809890 | Systems and methods for increasing yield of devices having cache memories by inhibiting use of defective cache entries Systems and methods for increasing the yield of devices incorporating set-associative cache memories by selectively avoiding the use of cache entries that include defects. In one embodiment, a cache replacement manager determines in which of n possible entries data ... | 10/05/2010 |
| 7808854 | Systems and methods for data transfers between memory cells Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair ... | 10/05/2010 |
| 7768326 | Wide range operational charge pump circuit A charge pump that includes cascode transistors and current mirror circuitry to form a folded cascode structure that isolates the control inputs from the charge pump output and also increases the range of the output. The charge pump includes inputs to receive UP and... | 08/03/2010 |
| 7748751 | Systems and methods for making connections between pipe sections to form a conduit that is substantially free of gaps Systems and methods for making connections between pipe sections. In one embodiment, a pipe connection consists of a pair of flanges having conically tapered sealing surfaces and a tapered seal ring. A first one of the flanges has a male nose extending forward from ... | 07/06/2010 |
| 7738483 | Systems and methods for managing communication between master and slave devices Systems and methods for increasing the efficiency of communications between master devices and slave devices in a system. A master normally sends a command to a slave if a token from the slave is received. Determining whether a token is of the correct type requires ... | 06/15/2010 |
| 7733717 | Memory system having distributed read access delays A system having a plurality of memory cells organized in rows and columns. Each column includes upper and lower sets of memory cells connected to corresponding common upper/lower bit lines. Each column includes an evaluation circuit coupled to the upper and lower bi... | 06/08/2010 |
| 7725897 | Systems and methods for performing real-time processing using multiple processors Systems and methods for increasing utilization of processors in a multiprocessor system by defining a strict real-time schedule and a pseudo-real-time schedule and dynamically switching between the strict real-time schedule and the pseudo-real-time schedule for exec... | 05/25/2010 |
| 7725686 | Systems and methods for processing buffer data retirement conditions Systems and methods for determining whether to retire a data entry from a buffer using multiple retirement logic units. In one embodiment, each retirement unit concurrently evaluates retirement conditions for one of the buffer entries in an associated subset (e.g., ... | 05/25/2010 |
| 7722538 | Conductance-imaging catheter and determination of cavitary volume Systems and methods for calibrating calculations based on catheter-originated measurements. One embodiment comprises a method for calibrating volume calculations for a fluid-filled cavity, such as a heart chamber. In this method, a first catheter configured to measu... | 05/25/2010 |
| 7701226 | Systems and methods for determining the state of a programmable fuse in an IC Systems and methods for detecting the mode (a.k.a., state) of a fuse or set of fuses in a device such as an integrated circuit. One embodiment comprises a method for determining three fuse states (uncut, cut, and destroyed) by comparing the fuse voltage with two ref... | 04/20/2010 |
| 7685458 | Assigned task information based variable phase delayed clock signals to processor cores to reduce di/dt Systems and methods for managing power consumption in an integrated circuit to reduce the rate of change of current (di/dt) in the integrated circuit. One embodiment comprises a system having multiple processor cores. A timing system provides each of the processor c... | 03/23/2010 |
| 7685156 | Systems and methods for rule inheritance Systems and methods for automating and increasing the efficiency of access to data using inheritance of access rules within an organization based upon the relationship of positions within the organization and the roles associated with the positions. In one embodimen... | 03/23/2010 |
| 7681158 | Delay budget allocation with path trimming Systems and methods for determining delay budget allocations for circuit elements. One embodiment comprises a method including defining timing edges and corresponding timing paths in an integrated circuit design, and determining delay budget allocations for each of ... | 03/16/2010 |
| 7681098 | Systems and methods for improved fault coverage of LBIST testing Systems and methods for improved fault coverage of logic built-in-self-tests (LBISTs) in integrated circuits (ICs) by determining weighting and/or seed values to be used in generating pseudorandom test bit patterns for each channel to optimize fault coverage. In one... | 03/16/2010 |
| 7669804 | Spacecraft interface module for enabling versatile space platform logistics support Systems and methods to deliver crew, cargo and other logistics services to space platforms. In one embodiment, a rendezvous and docking vehicle (RDV) comprises two docking mechanisms coupled to the RDV body. A pressurizable passageway connects the docking mechanisms... | 03/02/2010 |
| 7642868 | Wide range interpolative voltage controlled oscillator Systems and methods for increasing the frequency range of an output signal generated by a VCO, where one or more variable delay units are incorporated into an interpolative VCO to decrease the minimum frequency at which the VCO oscillates. In one embodiment, the VCO... | 01/05/2010 |
| 7642863 | Systems and methods for PLL linearity measurement, PLL output duty cycle measurement and duty cycle correction Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the fr... | 01/05/2010 |
| 7631237 | Multi-test method for using compare MISR Systems and methods for performing logic built-in-self-tests (LBISTs) where data comparisons are performed in the MISR. In one embodiment, a STUMPS-type LBIST architecture includes scan chains interposed between portions of the functional logic of the logic circuit.... | 12/08/2009 |
| 7631149 | Systems and methods for providing fixed-latency data access in a memory system having multi-level caches Systems and methods for bypassing lower level caches and enabling direct access to higher level caches in order to provide fixed data latency and increased amounts of immediately accessible storage. One embodiment comprises a memory system having multiple cache memo... | 12/08/2009 |
| 7627798 | Systems and methods for circuit testing using LBIST Systems and methods for performing logic built-in-self-tests (LBISTS) in digital circuits. In one embodiment, the operation of LBIST circuitry is suspended at the end of each test cycle so that the bit patterns generated by the functional logic of the device under t... | 12/01/2009 |
| 7613859 | Back-off timing mechanism in a digital signal processor Systems and methods for implementing back-off timing for retries of commands sent from a master device to a slave device over a split-transaction bus. One embodiment includes a buffer having entries for storing each pending command and associated information, includ... | 11/03/2009 |
| 7613841 | Systems and methods for reducing data storage in devices using multi-phase data transactions Systems and methods for enforcing in-order execution of commands sent from a master device to a slave device, where it is not necessary to provide a data buffer to store data associated with commands that are delayed to enforce in-order execution. In one embodiment,... | 11/03/2009 |
| 7607896 | Systems and methods for power ride-through in variable speed drives Systems and methods for providing ride-through for interruptions in the power supplied to drives that are used to control equipment such as downhole submersible pumps. In one embodiment, a variable speed drive includes converter and inverter sections, a capacitor ba... | 10/27/2009 |
| 7607059 | Systems and methods for improved scan testing fault coverage Systems and methods for improved fault coverage of logic built-in-self-tests (LBISTs) in integrated circuits (ICs) which ensure testing of specific logic by forcing specific values into scan latches that contain otherwise pseudorandom test bit patterns. In one embod... | 10/20/2009 |
