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| Number | Title | Issue Date |
| 5530674 | Structure capable of simultaneously testing redundant and non-redundant memory elements during stress testing of an integrated circuit memory device The redundant elements of an integrated circuit memory device having a plurality of redundant and non-redundant elements such as rows, columns, wordlines, and blocks, may be selectively enabled during a stress test mode so that both redundant elements and... | 06/25/1996 |
| 5517455 | Integrated circuit with fuse circuitry simulating fuse blowing Fuse circuitry is presented which emulates fuse blowing in a temporary manner. As an embodiment, redundant elements of an integrated circuit may be enabled and/or tested prior to laser repair through the use of non-destructive fuse circuitry which emulate... | 05/14/1996 |
| 5513143 | Data cache memory internal circuitry for reducing wait states The mechanism for performing writes to the data cache memory in a cache subsystem is modified to reduce the occurrence of microprocessor wait states. Concurrently, with operation of the tag RAM, the write signal from the microprocessor propagates through ... | 04/30/1996 |
| 5508679 | FIFO with adaptable flags for changing system speed requirements Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status through the use of programmable, resettable counters which eliminate the need for subtractor circuitry. A comparator is used to compare a value from a... | 04/16/1996 |
| 5502678 | Full memory chip long write test mode According to the present invention, a first memory block of the memory chip is placed into the long write test mode, meaning that all wordlines of the first memory block are turned off and the voltages on all the bitlines of the first memory block are con... | 03/26/1996 |
| 5502416 | Adjustable reset threshold for an integrated regulator According to the present invention, an integrated regulator having an adjustable reset threshold is disclosed. The integrated regulator has the following elements contained within an integrated circuit device: a transistor, a voltage reference block, an i... | 03/26/1996 |
| 5500603 | Methodology to quickly isolate functional failures associated with integrated circuit manufacturing defects According to the present invention, the functionality and possible process-related defects of an integrated circuit device are quickly assessed and isolated using a special testing methodology. Utilizing a test chip, an Electron Beam (E-Beam) is used to l... | 03/19/1996 |
| 5495446 | Pre-charged exclusionary wired-connected programmed redundant select Therefore, according to the present invention, replacement of defective elements of an integrated circuit memory device by a redundant array is accomplished using a redundant decode scheme which is as fast as or faster than the standard decode. An exclusi... | 02/27/1996 |
| 5491889 | Apparatus for achieving printed circuit board planarity According to the present invention, a system for placing surface mount components on a planar PCB has a placement apparatus which picks up a surface mount component to be placed on the PCB and moves it along the x and y axes to the desired PCB component l... | 02/20/1996 |
| 5491663 | Pre-charged slave latch with parallel previous state memory According to the present invention, a method and structure for using precharged data path techniques in those applications where it is necessary to retain the previous state of data is presented. In the preferred embodiment, a Pre-Charged Slave Latch with... | 02/13/1996 |
| 5471431 | Structure to recover a portion of a partially functional embedded memory According to the present invention, one or more addresses are forced to a logic state to define a smaller, fully functional portion of embedded memory. A first preferred embodiment has a first fuse circuit and a second fuse circuit which control the condu... | 11/28/1995 |
| 5465233 | Structure for deselecting broken select lines in memory arrays According to the present invention, a structure for holding broken select lines in a memory array deselected addresses the prior art problems associated with floating broken select lines, such as standby current and disruption of attached memory cells. Th... | 11/07/1995 |
| 5457647 | Passive hierarchical bitline memory architecture which resides in metal layers of a SRAM array In a high density memory, such as a SRAM, DRAM, EPROM or EEPROM, a hierarchical bitline configuration is utilized such that a number of local bitlines are connected to a master bitline through interface circuitry which connects a local bitline to the mast... | 10/10/1995 |
| 5455799 | Circuit which provides power on reset disable during a test mode According to the present invention, a special operating mode of an integrated circuit device, such as a stress test mode, is entered while the integrated circuit device is powered up in order to avoid the large switching transients from multiple rows and ... | 10/03/1995 |
| 5446698 | Block decoded redundant master wordline According to the present invention, defective element(s), such as a faulty local wordline, of an integrated circuit memory device may be selectively replaced with redundant element(s) in an efficient and flexible manner that does not require replacement o... | 08/29/1995 |
| 5432129 | Method of forming low resistance contacts at the junction between regions having different conductivity types A thin film transistor structure having a first and a second polycrystalline silicon layer of different conductivity types (P and N) has a high resistance contact at the resultant P-N junction. This contact resistance is reduced by forming TiSi2 | 07/11/1995 |
| 5428311 | Fuse circuitry to control the propagation delay of an IC According to the present invention, integrated circuitry provides for the ability to selectively introduce delays into the timing of the integrated circuit, without the expense and time associated with methods used in the prior art. As a minimum, a fuse e... | 06/27/1995 |
| 5424676 | Transistor collector structure for improved matching and chokeless power supply connection Internal to the transistor, an additional, direct connection is made from the internal collector to the external collector of the transistor by a fixed shunt inductance. The external power supply Vs is applied to the transistor collector throug... | 06/13/1995 |
| 5422595 | Miniature, low cost power amplifier monitor According to the present invention, a power amplifier with a plurality of power transistors has detection circuitry corresponding to each power transistor which detects the output power of the power transistors and allows this output power to be monitored... | 06/06/1995 |
| 5416032 | Method of making a high conductivity p-plus region for self-aligned, shallow diffused, bipolar transistors According to the present invention, using an emitter-P+ (E-P) mask, a low resistance, high conductivity P+ region of a self-aligned bipolar transistor device is formed prior to the formation of a base region. The P+ dif... | 05/16/1995 |
| 5400007 | Multiple level parallel magnitude comparator A magnitude comparator is modified to compare the magnitudes of two large binary values more quickly and with minimum gate delays. Bit comparators are divided into groups which generate compare output signals in parallel to one another, thereby reducing m... | 03/21/1995 |
| 5381126 | Programmable difference flag logic Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status through the use of programmable, resettable counters which eliminate the need for subtractor circuitry. A comparator is used to compare a value from a... | 01/10/1995 |
| 5379260 | Memory cell having a super supply voltage According to the present invention, a static random access memory (SRAM) cell which is normally supplied with a nominal supply voltage under normal operating conditions, may be supplied with a super supply voltage so that tests requiring high voltages and... | 01/03/1995 |
| 5357236 | Parallelized difference flag logic Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status without the use of subtractor circuitry. Bit comparators, which determine if a first bit is less than, equal to, or greater than a second bit, of a ma... | 10/18/1994 |
| 5357235 | Parallelized magnitude comparator A magnitude comparator suitable for use in a FIFO memory is modified to compare the magnitudes of two values more quickly. Bit comparators are divided into groups which generate compare output signals in parallel to one another, thereby reducing total mag... | 10/18/1994 |
| 5355344 | Structure for using a portion of an integrated circuit die Two addresses of an integrated circuit are selected to define a portion of the die which is functional and the portion of the die which will not be used. An input structure for addresses, which may be added to part of the electrostatic discharge (ESD) inp... | 10/11/1994 |
| 5319347 | Parallelized magnitude comparator for comparing a binary number to a fixed value A magnitude comparator suitable for use in a FIFO memory is modified to compare the magnitudes between any binary number and a fixed value. Bit comparators are divided into groups which generate compare output signals in parallel to one another, thereby r... | 06/07/1994 |
| 5315156 | Transistor device layout A modified transistor layout allows operation at high frequencies without adversely effecting transistor power gain. The base and collector circuits are modified in order to minimize ground bar resistance and feedback problems between the input and output... | 05/24/1994 |
