Quotables
"What can be more palpably absurd than the prospect held out of locomotives traveling twice as fast as stagecoaches?"
The Quarterly Review ; March edition, 1825
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| Number | Title | Issue Date |
| 6609190 | Microprocessor with primary and secondary issue queue A processor and data processing system suitable for dispatching an instruction to an issue unit. The issue unit includes a primary issue queue and a secondary issue queue. The instruction is stored in the primary issue queue if the instruction is currentl... | 08/19/2003 |
| 6549971 | Cascaded differential receiver circuit A differential receiver circuit including first, second, and third amplification stages. The first amplification stage is configured to receive a differential input signal and to produce a single ended first output signal responsive to the differential in... | 04/15/2003 |
| 6549927 | Circuit and method for summing multiple binary vectors A method and circuit for summing multiples vectors is disclosed. The method includes receiving a set of input vectors and generating a set of decoded summation vectors. Each of the set of decoded summation vectors indicates the value of at least a portion... | 04/15/2003 |
| 6543002 | Recovery from hang condition in a microprocessor A processor and an associated method and data processing system are disclosed. The processor includes an issue unit (ISU), a completion unit, and a hang detect unit. The ISU is configured to issue instructions to an execution unit. The completion unit is ... | 04/01/2003 |
| 6523151 | Method for verifying the design of a microprocessor A method for verifying an integrated circuit design includes generating verification coverage information by simulating the operation of the integrated circuit. The verification coverage information is then analyzed to determine a set of missing coverage ... | 02/18/2003 |
