Did You Know...
...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6070233 | Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in higher level cache A small first level cache and large second level cache support a central processor in accessing necessary data for processing. The second level cache holds tag address words each having two status bits V and R. The V bit indicates validity/invalidity stat... | 05/30/2000 |
| 5935200 | Exponential functional relationship generator method and system for implementation in digital logic A system and method for developing a digital control signal Y for setting a target module (D) according to a digital setpoint signal A, a digital feedback signal C, a difference digital signal X=A-C in an exponential relationship, such that Y=2X+1 | 08/10/1999 |
| 5928310 | Digital device control method and system via linear function generator implementation using adder for intercept A system and method in a digital network for developing a digital output control signal Y which is of greater range and sensitivity than an input digital difference signal X wherein Y has a linear functional relationship to X according to a slope paramete... | 07/27/1999 |
| 5920892 | Method and system for inhibiting transfer of duplicate write addresses in multi-domain processor systems with cross-bus architecture to reduce cross-invalidation requests A two domain digital network with each domain having its own system bus and its own bus exchange module permits Write operation addresses to be passed between domains. Each bus exchange module provides a match filter which prevents the passage from one bu... | 07/06/1999 |
| 5911776 | Automatic format conversion system and publishing methodology for multi-user network A network providing a server using an object-database enables an author to create and store an original document, as a source file with a first format. Software in the data base will provide multiple sets of shadow file-converter groups connected to the s... | 06/15/1999 |
| 5889959 | Fast write initialization method and system for loading channel adapter microcode A computer network serviced by a maintenance subsystem holds a control processing module (CPM) holding a Data Path Array as interface to a main memory module and I/O Module. A maintenance controller in the CPM has a preloaded Flash Memory unit holding all... | 03/30/1999 |
| 5850513 | Processor path emulation system providing fast readout and verification of main memory by maintenance controller interface to maintenance subsystem A central processing module (CPM) uses a data path array interface connecting dual system busses to a main memory module and I/O module. A maintenance controller in the CPM manages a programmable array logic unit controller to read out microcode words in ... | 12/15/1998 |
| 5848415 | Selective multiple protocol transport and dynamic format conversion in a multi-user network A content server using an object database supports a network of multiple User clients. The database is loaded with virtual objects which constitute source documents in the form of a multiplicity of resource objects, which may be file-oriented objects or m... | 12/08/1998 |
| 5845324 | Dual bus network cache controller system having rapid invalidation cycles and reduced latency for cache access A computer architecture where a processor with store-through cache is linked with a cache control module, a bus interface to dual system busses, a system spy module monitoring the dual system busses for new data overwrites and an invalidation queue for ho... | 12/01/1998 |
| 5842003 | Auxiliary message arbitrator for digital message transfer system in network of hardware modules A hardware message transfer control unit designated as the Auxiliary Message Arbitrator Unit (AMA) manages message transfers and transfer protocols in a network of sending and receiving digital hardware modules. Flexibility of network expansion to include... | 11/24/1998 |
| 5832250 | Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bits A multi-set cache structure, providing a first-level cache and second level cache to a processor, stores data words where each word holds two bytes and two status bits. Each cache set includes a Tag RAM for holding the address data words and a Parity RAM ... | 11/03/1998 |
| 5822334 | High speed initialization system for RAM devices using JTAG loop for providing valid parity bits A computer network having a Control Processing Module (CPM) maintained by an external Maintenance Subsystem where the CPM has JTAG compatible digital units, but where the Cache Module is not JTAG compatible. Specialized transceivers having Boundary Scan R... | 10/13/1998 |
| 5809533 | Dual bus system with multiple processors having data coherency maintenance A multi-module network having dual system busses using a common bus protocol which supports processor modules using a store-through cache memory and processor modules using a non-store-through cache memory which includes interface modules including a spy ... | 09/15/1998 |
| 5790813 | Pre-arbitration system allowing look-around and bypass for significant operations A system and method for setting the sequence of processor operations in real time depending on the nature of Write commands and Send Message Commands in waiting queues which are ordinarily sequenced with Read OPs according to the sequential order that the... | 08/04/1998 |
| 5768299 | Derived generation system for parity bits with bi-directional, crossed-fields utilizing stored flip-bit feature A network in which an incoming word of 4 bytes and 4 parity bits is split into an address pointer and Tag address data into a Tag RAM storing two bytes which do not align with the incoming bytes and which leave a 2-bit (x,y,) crossed field. A programmable... | 06/16/1998 |
| 5761445 | Dual domain data processing network with cross-linking data queues and selective priority arbitration logic A two domain network linking a first and second data processing system enables efficient data transfers between modules in the first system and modules in the second system through linkage by bus exchange modules having message queues and snoop-write addr... | 06/02/1998 |
| 5737567 | Fast write initialization system for microcode RAM via data path array using pre-loaded flash memory an programmable control logic array A network comprising a central processing module and maintenance subsystem which provides a system for rapid loading of instruction words in a microcode RAM whereby microcode instruction words from the maintenance subsystem are preliminarily loaded into a... | 04/07/1998 |
| 5737756 | Dual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queue A system and method for enhancing the rapidity of invalidation cycles in a processor having store-through cache holding 4-word data packets whereby an invalidation queue holds addresses of data to be invalidated in cache and the addresses are supplied by ... | 04/07/1998 |
| 5729712 | Smart fill system for multiple cache network An optimization system for the cache-fill operation in a multi-set cache memory operates to select that cache-set which indicates it has invalid data therein and/or also indicates that an associated upper level cache has correspondingly invalid data. When... | 03/17/1998 |
| 5717900 | Adjusting priority cache access operations with multiple level priority states between a central processor and an invalidation queue A computer network is connected via dual system busses to multiple digital modules such as a Central Processing Module with a Central Processor and also to a main memory module, plus an I/O module in addition to other possible modules, such as other Centr... | 02/10/1998 |
| 5717872 | Flexible, soft, random-like counter system for bus protocol waiting periods An initiator-sending module requests bus access on a retry-basis after a "bus-error" or "receiver-not ready" situation. The bus request retry is provided with an adjustable wait delay period tailored to the specific system and provides a programmable rand... | 02/10/1998 |
| 5708773 | JTAG interface system for communicating with compliant and non-compliant JTAG devices A system and method for using standard JTAG protocol for testing protocol compliant and non-protocol compliant digital devices without altering the JTAG protocol or the non-compliant device. A specialized Test Access Port Controller controls and monitors ... | 01/13/1998 |
| 5706446 | Arbitration system for bus requestors with deadlock prevention An arbitration logic system in a system control module regulates access to a common system bus as provided by a state machine which toggles access priority between two or more resource modules while preventing deadlock contention between two requesting mo... | 01/06/1998 |
| 5706297 | System for adapting maintenance operations to JTAG and non-JTAG modules A digital system which normally initializes and tests non-JTAG logic units is adapted to test JTAG protocol compatible logic units. A JTAG translator unit provides an instruction control register and a Data Register. The Control Register has control bits ... | 01/06/1998 |
| 5706424 | System for fast read and verification of microcode RAM A system whereby a microcode RAM in a central processing module can have each microcode word rapidly accessed and transferred to a maintenance controller to compare each accessed microcode word with a corresponding microcode word in a set of microcode wor... | 01/06/1998 |
| 5701431 | Method and system for randomly selecting a cache set for cache fill operations A central processor is serviced by a multi-way cache module having N cache sets some of which can be taken off-line by a maintenance subsystem. Masking logic is provided to control the fill-operation cycles to cache so that equitable distribution of fill-... | 12/23/1997 |
| 5699552 | System for improved processor throughput with enhanced cache utilization using specialized interleaving operations A system for interleaving invalidation cycles to a cache memory during those periods when the processor is waiting or has not need to access cache memory. These periods occur during a Read-Miss operation or when bus access delays to main memory cause the ... | 12/16/1997 |
| 5696937 | Cache controller utilizing a state machine for controlling invalidations in a network with dual system busses A state machine system is used to control a cache controller in a network involving the operations of a processor having a store-through cache and operations involving an invalidation queue which is filled by a spy module which monitors dual system busses... | 12/09/1997 |
| 5687348 | Variable-depth, self-regulating cache queue flushing system A FIFO invalidation queue for address words, from a spy module, are held for subsequent invalidation operations to a cache memory. The FIFO queue is programmably organized to indicate when it is almost full in which case it will switch to a priority opera... | 11/11/1997 |
| 5671400 | Programmable bus interface unit data path A field programmable gate array circuit device provides a bus interface data path between a processor and system bus, each of which operates at a different data transfer protocol at a different clock rate. The bus interface unit controls the transfer of d... | 09/23/1997 |
| 5666513 | Automatic reconfiguration of multiple-way cache system allowing uninterrupted continuing processor operation A multi-set cache module is initiated by a maintenance subsystem to function with all sets on-line or only some sets on-line. A parity error sensing switch flip-flop unit will selectively disable only those sets which indicate parity error problems except... | 09/09/1997 |
| 5644733 | Dual coupled partitionable networks providing arbitration logic for managed access to commonly shared busses Two partitioned systems are interconnected by bus exchange modules which connect to first and second system common busses. Each system common bus shares three or more requestors, and an arbitration logic unit in each partition manages bus access priority ... | 07/01/1997 |
| 5644579 | Bi-directional data transfer system enabling forward/reverse bit sequences A maintenance interface system for testing the Logic states of circuitry in digital modules provides for selecting a snake data path and using its control to Write into or to Read out in a forward sequence or selectively in a reverse sequence.... | 07/01/1997 |
| 5640531 | Enhanced computer operational system using auxiliary mini-cache for enhancement to general cache An enhanced computer system architecture provides a processor supported by a general cache and a mini-cache wherein the mini-cache will supply requested data words not available in the general cache thus eliminating the extra clock periods necessary to ac... | 06/17/1997 |
| 5634108 | Single chip processing system utilizing general cache and microcode cache enabling simultaneous multiple functions A microcode cache memory is provided on a processor chip for supplying frequently used microcode instruction words to a processor. A bank of multiple Tag-Status RAMs holds addresses of microcode words residing in a bank of Data RAMs. A state machine and a... | 05/27/1997 |
| 5598551 | Cache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cycles By expanding the cache address invalidation queue into bit slices for holding odd invalidation addresses and even invalidation addresses and also by providing a more efficient series of transition cycles to accomplish cache address invalidations both duri... | 01/28/1997 |
| 5598421 | Method and system for tracking the state of each one of multiple JTAG chains used in testing the logic of intergrated circuits The logic circuitry of an IC chip is connected to JTAG register chains which hold state information on each portion of the logic circuitry therein. A JTAG Tracker Module is connected to the controls of each of the JTAG register chains enabling a programme... | 01/28/1997 |
| 5581790 | Data feeder control system for performing data integrity check while transferring predetermined number of blocks with variable bytes through a selected one of many channels Multiple numbers of "sets" of sender-receiver units operate concurrently to transfer blocks of data. The number of blocks to be transferred in each set is predetermined by a main host computer which registers the number-of-blocks-to-be-transferred into a ... | 12/03/1996 |
| 5577201 | Diagnostic protocol and display system A diagnostic protocol and display system wherein the cable bus output of a computer to a printer is sensed to select coded error data out of the output stream in order to activate a visual display of coded error data for benefit of the human operator.... | 11/19/1996 |
| 5574865 | System for data transfer protection during module connection/disconnection onto live bus A plurality of digital modules on a Futurebus Plus common system bus means in a network are connected by the Futurebus Plus system bus for transfer of data between modules. A sending module (master) transmits address and message data on the bus to a recei... | 11/12/1996 |
