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| Number | Title | Issue Date |
| 5444860 | Translator system for message transfers between digital units operating on different message protocols and different clock rates A message transfer system between digital modules where two or more digital modules operate on separate and different message lengths and clock frequencies and where, temporary storage buffer (translator unit) holds messages being transferred between the ... | 08/22/1995 |
| 5337414 | Mass data storage and retrieval system A mass storage/retrieval module for controlling the storage and retrieval operations of massive amounts of data in peripheral devices such as tape, disk, optical, etc. provides for a buffer memory system in each of the interface control modules which perm... | 08/09/1994 |
| 5321816 | Local-remote apparatus with specialized image storage modules An apparatus provides a network combining a local site having a host computer and a specialized storage and retrieval module for storing image information which is connected to a remote site having document processing equipment working with remote special... | 06/14/1994 |
| 5321814 | System for optional module detection and reconfiguration An automatic re-configurable computer system having a standard processor module and standard main memory and I/O control modules where each module is inter-connected to a common system bus. Automatic re-configuration occurs in the standard modules, when a... | 06/14/1994 |
| 5301350 | Real time storage/retrieval subsystem for document processing in banking operations A storage/retrieval module apparatus for use in a document imaging system can receive digitized optical image and related information data, convert it to electrical digital data for storage on disk at high rates of speed. Concurrently with storage operati... | 04/05/1994 |
| 5287497 | Image statement printing system with document storage/retrieval using optical media A storage/retrieval system providing a two month digital data accumulation in archival storage and a one month digital data accumulation storage (for monthly statements) of document images and information. A Master Print Index File correlates data on each... | 02/15/1994 |
| 5283882 | Data caching and address translation system with rapid turnover cycle An address couple associateive memory (ACAM) for a processor in a chip package provides a first address couple (ACL) CAM and a second absolute address list (AAL) CAM. An associated control unit guarantees coherency of word data in a cache RAM and main mem... | 02/01/1994 |
| 5241547 | Enhanced error detection scheme for instruction address sequencing of control store structure A control store holding a large number of instruction words is accessed by a sequence of instruction addresses. An intercooperating system uses a test condition select logic unit and a next address select logic unit are combined with address sequence erro... | 08/31/1993 |
| 5226005 | Dual ported content addressable memory cell and array An improved CAM (content addressable memory) cell is provided with dual address lines operable independently for a Read operation or for a Write operation. The cell is additionally provided with dual ports so that the first port permits a data input for W... | 07/06/1993 |
| 5219145 | Adjustably deflectable spring plate device An apparatus for minimizing bending distortion in base support planes of tray units holding weighted modules. A cut out flap in the base plane is set at an angle to form a deflection spring plate against the module weight. The angle is adjustable to opera... | 06/15/1993 |
| 5187750 | Archival document image processing and printing system A document processing, archival storage and printout system such as for handling customer checking accounts. Original checks/documents are processed into digital image data then stored temporarily in magnetic media and transferred to optical long-term arc... | 02/16/1993 |
| 5170466 | Storage/retrieval system for document A high-capacity high-speed storage/retrieval system for storage and retrieval of document images in digitized data form permits clusters of storage/retrieval modules (SRM's) to store and exchange digital data via local area networks within the cluster of ... | 12/08/1992 |
| 5146596 | Multiprocessor multifunction arbitration system with two levels of bus access including priority and normal requests Arbitration and control circuitry for monitoring the two processors sharing a system bus to insure fair access to system resources and to sense error conditions which occur in order to hold access for the processor involved until the error condition is cl... | 09/08/1992 |
| 5142627 | FIP-compliant block multiplexor channel interface operational method for cache/disk subsystem A procedure, enabled in software, and applied to a cache/disk environment controlled by a host computer operating through a Block Multiplexor Channel Interface and Storage Control Unit, functions to use FIPS 97 and FIPS 60 protocols to execute data transf... | 08/25/1992 |
| 5134663 | Center line magnetic ink character recognition system A system and method for recognizing magnetic ink character records (MICR) by establishing a centerline between the first and last peaks of a scanned magnetic-electrical read out, which centerline is used to establish the location of the major peaks. Then ... | 07/28/1992 |
| 5113500 | Multiple cooperating and concurrently operating processors using individually dedicated memories A personal computer (PC) desktop workstation using a first operating system is enhanced with a single PC bus extension card (SCAMP Board) within its base housing which connects a second computer system (A-Series) having a large memory, control logic and a... | 05/12/1992 |
| 5088092 | Width-expansible memory integrity structure A width-expansible ROM/PROM memory structure includes a plurality of duplicate-type ROM/PROM data memory chips and includes a duplicate-type ROM/PROM parity memory chip. Stored data words of "n" bits can be stored in the memory chips and combined in outpu... | 02/11/1992 |
| 5087953 | Flexible gate array system for combinatorial logic A method and technique for inserting additive logic into the architecture of a gate array chip package whereby spare input and output pins can later be used to alter the logic functions by either disabling or enabling certain logic units internal to the c... | 02/11/1992 |
| 5087839 | Method of providing flexibility and alterability in VLSI gate array chips A method and technique for inserting additive logic and flip-flops into the architecture of a gate array chip package whereby spare input and output pins can later be used to alter the logic functions by either disabling or enabling certain logic units in... | 02/11/1992 |
| 5086427 | Clocked logic circuitry preventing double driving on shared data bus A system wherein multiple sources of data each have drivers for transmitting data to a common system bus. The drivers are each managed by individual enabling logic which is controlled by a flip-flop driven by a clock. Thus no driver can connect and drive ... | 02/04/1992 |
| 5063572 | Channelized delay and mix chip rate detector A detector circuit for indicating the chip rate of a direct sequence frequency hopped data transmission signal. The wide band input signal is channelized into L adjacent sub-bands and each sub-band signal is multiplied by a delayed copy of itself and then... | 11/05/1991 |
| 5052001 | Multiple memory bank parity checking system A ROM/PROM memory system circuit structure provides for vertical expansion of data words while providing for enablement of parity checking by the addition of a single auxiliary ROM/PROM memory chip which duplicates the type and size of data memory chips. ... | 09/24/1991 |
| 5025365 | Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors This disclosure describes a snooping coherency protocol for a multiprocessor network wherein every processor has its own private cache and bus interface means and the network is connected via a common system bus. Each processor has its own cache directory... | 06/18/1991 |
