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...Daniel Webster invented a "bull plow" to pull out tree stumps. It didn't catch on because it was huge and required four oxen to pull it!
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| Number | Title | Issue Date |
| 8141086 | Using data in elements of a singly linked list without a lock in a multithreaded environment A method and system for validating a scan of a chain in a multithreaded environment. A modification counter and an anchor address are atomically copied from the chain's header into a first variable (browse counter) and second variable, respectively. The second varia... | 03/20/2012 |
| 8140372 | Planning production for complementary demands Method, system and program product for planning production for complementary demands are disclosed. In one embodiment, a method includes obtaining complementary demand values including at least one daily going rate (DGR) demand and a service demand; running a first ... | 03/20/2012 |
| 8138099 | Chip package solder interconnect formed by surface tension Disclosed herein is a solder self-assembly structure, an IC chip including a solder self-assembly structure, and a method of making the same. The structure includes a release layer disposed on a portion of an upper surface of the substrate, laterally spaced from a v... | 03/20/2012 |
| 8138008 | Forming an oxide MEMS beam Solutions for forming a semiconductor including an oxide MEMS beam are disclosed. In one embodiment, a method of forming a beam within a sealed cavity includes: depositing a lower insulator layer comprising one or more layers; depositing an upper insulator layer ove... | 03/20/2012 |
| 8125007 | Integrated circuit including FinFET RF switch angled relative to planar MOSFET and related design structure An integrated circuit (IC) includes a fin field effect transistor (FinFET) radio frequency (RF) switch; and a planar complementary metal-oxide semiconductor field effect transistor (MOSFET). The planar MOSFET has a channel on a wafer plane and the FinFET RF sw... | 02/28/2012 |
| 8112729 | Method and system for selective stress enablement in simulation modeling A method and system for modeling an integrated circuit. The method includes converting a representation of the integrated circuit into design shapes of design levels of a design of the integrated circuit; adding control shapes to the design, the control shapes not d... | 02/07/2012 |
| 8112579 | Selecting a destination tape recording device for saving data Selecting a destination tape recording device, out of a plurality of tape recording devices, for saving data. Particularly a technique for selecting a tape recording apparatus whose performance is optimal for data to be saved, thereby improving data backup performan... | 02/07/2012 |
| 8106513 | Copper damascene and dual damascene interconnect wiring A copper corrosion resistant integrated circuit. The integrated circuit including: a substrate; a copper diffusion barrier layer on the substrate; a dielectric layer on a top surface of the copper diffusion barrier layer; a copper damascene or dual damascene wire in... | 01/31/2012 |
| 8106457 | Silicon-on-insulator based radiation detection device and method Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the bu... | 01/31/2012 |
| 8088690 | CMP method The instant invention is a method of polishing a substrate including contacting a substrate having at least one metal layer including copper with a chemical-mechanical polishing composition. The CMP composition includes an abrasive, a surfactant, an oxidizer, an org... | 01/03/2012 |
| 8039376 | Methods of changing threshold voltages of semiconductor transistors by ion implantation A method for forming a semiconductor structure. The method includes providing a semiconductor structure including a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top... | 10/18/2011 |
| 8035200 | Neutralization of trapped charge in a charge accumulation layer of a semiconductor structure A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical... | 10/11/2011 |
| 8035198 | Through wafer via and method of making same A through wafer via structure. The structure includes: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically n... | 10/11/2011 |
| 8026606 | Interconnect layers without electromigration A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing... | 09/27/2011 |
| 8021803 | Multi-chip reticle photomasks A multi-chip reticle, methods of designing and fabricating multi-chip reticles, a system for designing a multi-chip reticle, and a method of fabricating integrated circuit chips using the multi-chip reticle. The multi-chip reticle includes a transparent substrate ha... | 09/20/2011 |
| 8017995 | Deep trench semiconductor structure and method An electrical structure and method of forming. The electrical structure includes a semiconductor substrate comprising a deep trench, an oxide liner layer is formed over an exterior surface of the deep trench, and a field effect transistor (FET) formed within the sem... | 09/13/2011 |
| 8017514 | Optically transparent wires for secure circuits and methods of making same A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; ... | 09/13/2011 |
| 8015526 | Static timing slacks analysis and modification A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is perf... | 09/06/2011 |
| 8013342 | Double-sided integrated circuit chips A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having d... | 09/06/2011 |
| 8010934 | Method and system for testing bit failures in array elements of an electronic circuit The invention relates to a method and system for testing bit failures in array elements of an electronic circuit. Said method comprising the steps of changing an original hardware representation (DD) of the array such that errors can be injected in a memory by manip... | 08/30/2011 |
| 8004289 | Wafer-to-wafer alignments Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The firs... | 08/23/2011 |
| 8004024 | Field effect transistor A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gat... | 08/23/2011 |
| 7989312 | Double-sided integrated circuit chips A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are ... | 08/02/2011 |
| 7982269 | Transistors having asymmetric strained source/drain portions A semiconductor structure. The structure includes (a) a fin region having (i) a first source/drain portion having a first surface and a third surface, wherein the first and third surfaces are (A) parallel to each other and (B) not coplanar, (ii) a second source/drai... | 07/19/2011 |
| 7981732 | Programming of laser fuse A method for programming a laser fuse. The laser fuse has a fuse link including a material having a characteristic of changing its electrical resistance after being exposed to a laser beam. The laser beam is directed to the fuse link, the laser beam being controlled... | 07/19/2011 |
| 7964466 | FinFET transistor and circuit A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at le... | 06/21/2011 |
| 7964465 | Transistors having asymmetric strained source/drain portions A structure formation method. First, a structure is provided including (a) a fin region comprising (i) a first source/drain portion having a first surface and a third surface parallel to each other, not coplanar, and both exposed to a surrounding ambient, (ii) a sec... | 06/21/2011 |
| 7960245 | Dual wired integrated circuit chips A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with fir... | 06/14/2011 |
| 7958484 | Affinity-based clustering of vectors for partitioning the columns of a matrix A method for partitioning the columns of a matrix A. The method includes providing the matrix A in a memory device of a computer system. The matrix A has n columns and m rows, wherein n is an integer of at least 3, and wherein m is an integer of at least 1. The meth... | 06/07/2011 |
| 7945887 | Modeling spatial correlations Modeling spatial correlations of semiconductor characteristic variations is disclosed. In one embodiment, a method includes developing a solution for each of a plurality of specific forms of spatial correlations of a characteristic of a circuit design and developing... | 05/17/2011 |
| 7939914 | Dual wired integrated circuit chips A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with fir... | 05/10/2011 |
| 7939390 | Gap capacitors for monitoring stress in solder balls in flip chip technology A semiconductor structure formation method and operation method. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plat... | 05/10/2011 |
| 7935604 | Method of making small geometry features A method of forming a small geometry feature. The method includes forming a source layer on a top surface of a substrate; forming a mandrel on a top surface of the source layer, the mandrel having a sidewall; sputtering material from the source layer onto the sidewa... | 05/03/2011 |
| 7935408 | Substrate anchor structure and method An electrical structure and method of forming. The electrical structure includes a first substrate, first dielectric layer, an underfill layer, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectr... | 05/03/2011 |
| 7921246 | Automatically identifying available storage components A method for automatically identifying available storage components within a storage system, which are appropriate for storing consumer data in compliance with specified service level objectives (SLOs), including discovering available storage components; identifying... | 04/05/2011 |
| 7917348 | Method of switching external models in an automated system-on-chip integrated circuit design verification system A system and method for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for se... | 03/29/2011 |
| 7911803 | Current distribution structure and method An electrical structure and method of forming. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive p... | 03/22/2011 |
| 7904868 | Structures including means for lateral current carrying capability improvement in semiconductor devices A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer grea... | 03/08/2011 |
| 7898045 | Passive electrically testable acceleration and voltage measurement devices Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second i... | 03/01/2011 |
| 7886245 | Structure for optimizing the signal time behavior of an electronic circuit design A design structure for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit designed by an IC design house or other circuit design provider. T... | 02/08/2011 |
