Kotulak, Esq.; Richard M. - US Patent Attorneys and Agents

Attorney: Kotulak, Esq.; Richard M.

Number of patents: 231
Last date: May 15, 2012

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Number	Title	Issue Date
8178434	On-chip embedded thermal antenna for chip cooling An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connect...	05/15/2012
8169007	Asymmetric junction field effect transistor A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and ...	05/01/2012
8168500	Double gate depletion mode MOSFET A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abut...	05/01/2012
8165913	System, method, program for assigning virtual attribute to product, and system, method, and program for tracing cause of phenomenon occurring in product A system for tracing a cause of a phenomenon occurring in products produced in a production process chain is provided. The system is provided with a storage unit for storing a virtual attribute in association with corresponding second products, a receiving unit for ...	04/24/2012
8140347	System and method for speeding XML construction for a business transaction using prebuilt XML with static and dynamic sections A system and method for constructing extensible markup language (XML) transactions comprising an XML format run on a computer system, wherein the method comprises pre-building static structures of an XML transaction, classifying dynamic structures of the XML transac...	03/20/2012
8135558	Automated simulation testbench generation for serializer/deserializer datapath systems Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are ada...	03/13/2012
8133774	SOI radio frequency switch with enhanced electrical isolation At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. Th...	03/13/2012
8129773	Fin-type field effect transistor Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance bet...	03/06/2012
8115251	Recessed gate channel with low Vt corner A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate diele...	02/14/2012
8114768	Electromigration resistant via-to-line interconnect A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal ...	02/14/2012
8114750	Lateral diffusion field effect transistor with drain region self-aligned to gate electrode A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alte...	02/14/2012
8101505	Programmable electrical fuse The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separat...	01/24/2012
8084858	Metal wiring structures for uniform current density in C4 balls In one embodiment, a sub-pad assembly of metal structures is located directly underneath a metal pad. The sub-pad assembly includes an upper level metal line structure abutting the metal pad, a lower level metal line structure located underneath the upper level meta...	12/27/2011
8080465	Semiconductor wafer structure with balanced reflectance and absorption characteristics for rapid thermal anneal uniformity Disclosed are embodiments of semiconductor wafer structures and associated methods of forming the structures with balanced reflectance and absorption characteristics. The reflectance and absorption characteristics are balanced by manipulating thin film interferences...	12/20/2011
8076204	Graphene-based transistor A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafte...	12/13/2011
8053901	Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k di...	11/08/2011
8053870	Semiconductor structure incorporating multiple nitride layers to improve thermal dissipation away from a device and a method of forming the structure Disclosed are embodiments of a semiconductor structure that incorporates multiple nitride layers stacked between the center region of a device and a blanket oxide layer. These nitride layers are more thermally conductive than the blanket oxide layer and, thus provid...	11/08/2011
8053814	On-chip embedded thermal antenna for chip cooling An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connect...	11/08/2011
8053348	Method of forming a semiconductor device using a sacrificial uniform vertical thickness spacer structure Disclosed is a method of forming planar and non-planar semiconductor devices using a sacrificial gate sidewall spacer with a uniform vertical thickness. The method forms such spacers by selectively growing an epitaxial film on the vertical sidewalls of a gate struct...	11/08/2011
8053314	Asymmetric field effect transistor structure and method Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide opt...	11/08/2011
8039929	Asymmetrically stressed CMOS FinFET A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region comprising a N+ ...	10/18/2011
8039356	Through silicon via lithographic alignment and registration A method of manufacturing an integrated circuit structure forms a first opening in a substrate and lines the first opening with a protective liner. The method deposits a material into the first opening and forms a protective material over the substrate. The protecti...	10/18/2011
8034699	Isolation with offset deep well implants A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is re...	10/11/2011
8032349	Efficient methodology for the accurate generation of customized compact model parameters from electrical test data Disclosed herein are embodiments of an automated, fast and efficient method of generating a customized compact model that represents a semiconductor device at the chip, wafer or multi-wafer level in a specific manufacturing environment. Specifically, measurement dat...	10/04/2011
8030687	Field effect transistor incorporating at least one structure for imparting temperature-dependent strain on the channel region and associated method of forming the transistor Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-depend...	10/04/2011
8022478	Method of forming a multi-fin multi-gate field effect transistor with tailored drive current Disclosed are embodiments of an improved multi-gated field effect transistor (MUGFET) structure and method of forming the MUGFET structure so that it exhibits a more tailored drive current. Specifically, the MUGFET incorporates multiple semiconductor fins in order t...	09/20/2011
8017997	Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor fie...	09/13/2011
8017934	Carbon nanotube based integrated semiconductor circuit Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Elect...	09/13/2011
8017489	Field effect structure including carbon alloyed channel region and source/drain region not carbon alloyed A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device structure. The field effect device structure includes a gate electrode located over a channel region within a semiconductor substrate that separates a pl...	09/13/2011
8015518	Structures for electrostatic discharge protection for bipolar semiconductor circuitry A design structure for electrostatic discharge protection comprises a first data representing a first electrostatic discharge (ESD) protection circuit and a second data representing a second ESD protection circuit. A parallel connection of two ESD protection units, ...	09/06/2011
8010916	Test yield estimate for semiconductor products created from a library Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield imp...	08/30/2011
8008748	Deep trench varactors A deep trench varactor structure compatible with a deep trench capacitor structure and methods of manufacturing the same are provided. A buried plate layer is formed on a second deep trench, while the first trench is protected from formation of any buried plate laye...	08/30/2011
8008146	Different thickness oxide silicon nanowire field effect transistors A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a firs...	08/30/2011
7996807	Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments in...	08/09/2011
7994612	FinFETs single-sided implant formation A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are...	08/09/2011
7989358	Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chi...	08/02/2011
7977714	Wrapped gate junction field effect transistor A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second co...	07/12/2011
7974802	Photomask image inspection A method optimizes photomask inspection. After masks are manufactured, the method predicts the likelihood that the masks will be defect free based on defect criteria, etch area, etch mode, and etch tool type associated with the masks. The method skips an initial mas...	07/05/2011
7972919	Vertical PNP transistor and method of making same The present invention relates to a device structure located in a semiconductor substrate and containing high performance vertical NPN and PNP transistors. Specifically, the vertical PNP transistor has an emitter region, and the vertical NPN transistor has an intrins...	07/05/2011
7966214	Method for considering hierarchical preemptive demand priorities in a supply chain optimization model The invention comprises a method for achieving consideration of preemptive priorities within a supply chain optimization model. More specifically, the invention provides a method of allocating resources to a hierarchy of demand priorities in a linear programming pro...	06/21/2011

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Attorney: Kotulak, Esq.; Richard M.