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| Number | Title | Issue Date |
| 8120966 | Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting dat... | 02/21/2012 |
| 8120959 | NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same A nonvolatile memory device includes a nonvolatile memory array including a plurality of charge retaining transistors arranged in rows and columns. The device has a plurality source lines formed in parallel with the bit lines associated with each column. Row decode/... | 02/21/2012 |
| 8072811 | NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device... | 12/06/2011 |
| 8059471 | Method and apparatus of operating a non-volatile DRAM A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-ga... | 11/15/2011 |
| 8058942 | Dual reference oscillator phase-lock loop A phase-locked loop has a stable high frequency reference oscillator to provide a stable high frequency reference signal that has reference frequency that is a small submultiple of a generated frequency of a voltage controlled oscillator within the phase-locked loop... | 11/15/2011 |
| 7957183 | Single bit line SMT MRAM array architecture and the programming method An SMT MRAM device includes a plurality of SMT MRAM cells arranged in an array of rows and columns. Single bit lines connect the columns of the SMT MRAM cells for receiving an in-phase data signal. Source lines connect pairs of rows of the SMT MRAM cells for receivi... | 06/07/2011 |
| 7855912 | Circuit and method for multiple-level programming, reading, and erasing dual-sided nonvolatile memory cell A control apparatus programs, reads, and erases trapped charges representing multiple data bits from a charge trapping region of a NMOS dual-sided charge-trapping nonvolatile memory cell includes a programming circuit, an erasing circuit, and a reading circuit. The ... | 12/21/2010 |
| 7852662 | Spin-torque MRAM: spin-RAM, array A spin-torque MRAM array has MRAM cells arranged in rows and columns. Bit lines are connected to each of the MRAM cells on each column. Source select lines are connected to each MRAM cell of a pair of rows and are oriented orthogonally to the bit lines. Write lines ... | 12/14/2010 |
| 7833814 | Method of forming pinned photodiode (PPD) pixel with high shutter rejection ratio for snapshot operating CMOS sensor A method for forming a pixel image sensor that has a high shutter rejection ratio for preventing substrate charge leakage and prevents generation of photoelectrons within a floating diffusion storage node and storage node control transistor switches of the pixel ima... | 11/16/2010 |
| 7830713 | Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array A nonvolatile memory structure with pairs of serially connected select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND se... | 11/09/2010 |
| 7796463 | Self-feedback control pipeline architecture for memory read path applications A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection a... | 09/14/2010 |
| 7782661 | Boosted gate voltage programming for spin-torque MRAM array A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device of the spin-torque MRAM cell. A spin-torque MRAM cell array is compose... | 08/24/2010 |
| 7688612 | Bit line structure for a multilevel, dual-sided nonvolatile memory cell array A nonvolatile memory array includes a plurality of dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells on each column form at ... | 03/30/2010 |
| 7680202 | Digital wireless audio communication system employing time diversity A communication system that transfers digital data on a fixed frequency channel of a radio frequency band in the presence of interference from at least one FHSS interference source includes a time diversity generation circuit. The time diversity circuit compacts a d... | 03/16/2010 |
| 7657041 | Laser audio preamplifier, volume control, and multiplexer A fiber optical audio preamplifier receives audio signals from an audio source, amplifies the audio signals, and transfers the signals to a power amplifier. The fiber optical audio preamplifier has at least one first signal converter. Each first signal converter acq... | 02/02/2010 |
| 7635974 | Magnetic tunnel junction (MTJ) based magnetic field angle sensor A magnetic field angle sensor for measurement of a magnetic field angle over a 360° range has magnetic tunnel junction elements oriented at multiple angles. The magnetic field angle sensor includes multiple magnetic tunnel junction elements formed on a substrate th... | 12/22/2009 |
| 7571673 | Method for treating a wine, measuring its aptitude for ageing and device for implementing said method Method and device for accelerating the ageing of a wine contained in an open or closed container comprising the following steps: putting a wine to be processed in contact with a silver, gold, and copper alloy element having a surfa... | 08/11/2009 |
| 7555031 | Digital wireless audio receiver system employing time diversity A receiver system that receives and recovers digital data on a fixed frequency channel of a radio frequency band in the presence of interference from at least one FHSS interference source. The digital data has a duration of data frames compacted then replicated to f... | 06/30/2009 |
| 7551806 | Two stage interpolation apparatus and method for up-scaling an image on display device A graphics display adapter has a row interpolator circuit connected to receive the source pixel data synchronized at a first clock rate and to interpolate groups of pixels of row at a second clock rate. A row interpolated storage device receives and retains interpol... | 06/23/2009 |
| 7551681 | Digital wireless audio transmitter system employing time diversity A transmitter system that transfers digital data on a fixed frequency channel of a radio frequency band in the presence of interference from at least one FHSS interference source includes a time diversity generation circuit. The time diversity circuit compacts a dur... | 06/23/2009 |
| 7548261 | Column averaging/row averaging circuit for image sensor resolution adjustment in high intensity light environment A photo-sensor image resolution adjustment apparatus is in communication with an array of image photo-sensors that are organized in columns and rows and have multiple sensor types arranged in a pattern such as a Bayer pattern to detect light. The photo-sensor image ... | 06/16/2009 |
| 7532817 | Fiber optic link protection apparatus A fiber optic protection apparatus includes a first optical switch, a first fault detection device, and first switch control device. The first optical switch is placed at the reception node of an optical link and has a primary input port connected to a primary optic... | 05/12/2009 |
| 7515183 | Column averaging/row binning circuit for image sensor resolution adjustment in lower intensity light environment A photo-sensor image resolution adjustment apparatus is in communication with an array of image photo-sensors that are organized in columns and rows and have multiple sensor types arranged in a pattern such as a Bayer pattern to detect light. The photo-sensor image ... | 04/07/2009 |
| 7515158 | Modularly configurable memory system for LCD TV system A configurable memory system provides a high bandwidth, low latency, no wait state data path to a memory system functioning as a frame buffer for a digital video processing system. The configurable memory system has configurable channels that are programmable to con... | 04/07/2009 |
| 7499314 | Reference cell scheme for MRAM An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines ... | 03/03/2009 |
| 7492849 | Single-VCO CDR for TMDS data at gigabit rate A clock and data recovery circuit has a voltage controlled oscillator that provides a clocking signal synchronized to a received serialized data. A multiple phase generator converts the clocking signal to a plurality of multiple phased clocking signals. A data captu... | 02/17/2009 |
| 7479994 | Image sensor having resolution adjustment employing an analog column averaging/row averaging for high intensity light or row binning for low intensity light A photo-sensor image resolution adjustment apparatus is in communication with an array of image photo-sensors that are organized in columns and rows and have multiple sensor types arranged in a pattern such as a Bayer pattern to detect light. The photo-sensor image ... | 01/20/2009 |
| 7480172 | Programming scheme for segmented word line MRAM array An MRAM array has a plurality of MRAM devices that are arranged in rows and columns with segmented word lines. A magnetic biasing field is coupled to each of the MRAM devices. The MRAM devices are programmed by providing a bidirectional bit line current to a selecte... | 01/20/2009 |
| 7457539 | 2×2 optical switch A 2×2 optical switch routs each light signal received from input ports to selected output. The optical switch has an adjustable light signal steering element, a fixed light signal steering element, and a steering element actuator. The adjustable light signal steeri... | 11/25/2008 |
| 7427734 | Multiple photosensor pixel A multiple photosensor pixel image sensor sense differentiated color components of light. The multiple photosensor pixel image sensor has a plurality of photo-sensing devices formed with the surface of the substrate. Each photo-sensing device has a structure adjuste... | 09/23/2008 |
| 7423302 | Pinned photodiode (PPD) pixel with high shutter rejection ratio for snapshot operating CMOS sensor A pixel image sensor has a high shutter rejection ratio that prevents substrate charge leakage to a floating diffusion storage node of the pixel image sensor and prevents generation of photoelectrons within the floating diffusion storage node and storage node contro... | 09/09/2008 |
| 7391656 | Self-feedback control pipeline architecture for memory read path applications A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection a... | 06/24/2008 |
| 7372736 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell... | 05/13/2008 |
| 7372162 | Multiple selectable function integrated circuit module An integrated circuit module has a common function known good integrated circuit die with selectable functions. The selectable functions are selected during packaging of the known good integrated circuit die. The known good integrated circuit die is mounted to a sec... | 05/13/2008 |
| 7369438 | Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications A combination volatile and nonvolatile memory integrated circuit has at least one volatile memory array placed on the substrate and multiple nonvolatile memory arrays. The volatile and nonvolatile memory arrays have address space associated with each other such that... | 05/06/2008 |
| 7362144 | Low jitter input buffer with small input signal swing A particular input buffer receiver includes a buffer input portion for receiving an input signal, a large capacitor between a bias node and the lower supply voltage, and a buffer output portion for producing an output signal. The circuit works to remove ground noise... | 04/22/2008 |
| 7360005 | Software programmable multiple function integrated circuit module An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input data signals. The outputs of the plurality of optionally selectable func... | 04/15/2008 |
| 7349679 | Integrated power amplifier A power amplifier develops a modulated high power signal by summing the outputs of multiple voltage controlled oscillators. A phase control circuit synchronizes the phase relationship of multiple voltage controlled oscillators. The voltage control oscillators provid... | 03/25/2008 |
| 7327919 | Fiber optic audio cable A signal transmission media for transmission of signals such as audio and/or video from a transmission apparatus to a receiving apparatus. The signal transmission media has a first connector in contact with the transmission apparatus to receive the signal and is com... | 02/05/2008 |
| 7324555 | Streaming while fetching broadband video objects using heterogeneous and dynamic optimized segmentation size An video data object distribution system for transfer of video data objects includes a network of digital data file servers. The network of digital data file servers communicate with a client system to transfer video data objects. A scheduling apparatus schedules th... | 01/29/2008 |
