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| Number | Title | Issue Date |
| 8180969 | Cache using pseudo least recently used (PLRU) cache replacement with locking A cache stores information in each of a plurality of cache lines. Addressing circuitry receives memory addresses for comparison with multiple ways of stored addresses to determine a hit condition representing a match of a stored address and a received address. A pse... | 05/15/2012 |
| 8145985 | Error detection schemes for a unified cache in a data processing system In a data processing system processing circuitry executes a plurality of data processing instructions. A unified cache memory stores data and instructions processed by the processing circuitry. The unified cache memory has a plurality of sets, each set having a plur... | 03/27/2012 |
| 8131951 | Utilization of a store buffer for error recovery on a store allocation cache miss A processor and cache is coupled to a system memory via a system interconnect. A first buffer circuit coupled to the cache receives one or more data words and stores the one or more data words in each of one or more entries. The one or more data words of a first ent... | 03/06/2012 |
| 8131948 | Snoop request arbitration in a data processing system A snoop look-up operation is performed in a system having a first cache and a first processor. The first processor generates access requests to the first cache for data. Snoop look-up operations are performed in the cache. The snoop look-up operations are based on s... | 03/06/2012 |
| 8131947 | Cache snoop limiting within a multiple master data processing system In a data processing system, access to a cache in response to access requests from first processing circuitry and snoop requests resulting from a transaction performed by second processing circuitry are arbitrated. Accesses to the cache are monitored to determine if... | 03/06/2012 |
| 8099560 | Synchronization mechanism for use with a snoop queue In a data processing system each bus master of a plurality of bus masters communicates information via a system interconnect. A cache is associated with a predetermined bus master of the plurality of bus masters for storing information used by the predetermined bus ... | 01/17/2012 |
| 8095831 | Programmable error actions for a cache in a data processing system A data processing system and method of operation has a processor coupled to a cache. Cache control circuitry is coupled to the cache and performs error detection. A user programmable error action control register stores a control value for selecting a type of error ... | 01/10/2012 |
| 8040700 | Charge pump for use with a synchronous load A charge pump has circuitry and implements a method for monitoring a synchronous load by using a first voltage threshold below a target output voltage and a second voltage threshold above a target output voltage. An output terminal is coupled to the load. Charge is ... | 10/18/2011 |
| 8014682 | Free-space optical communication system A free-space communication system and method of operation includes a first communication device physically coupled to a substrate and having an optical transmitter for communicating information. A second communication device is physically coupled to the substrate an... | 09/06/2011 |
| 8009397 | Method and circuit for eFuse protection An eFuse (electronic fuse) circuit has a first detector for determining whether an ESD (electrostatic discharge) event occurs at a circuit pad of an integrated circuit and provides an ESD trigger signal in response thereto. A second detector detects a presence of a ... | 08/30/2011 |
| 7992052 | Program correlation message generation for debug A data processing system and method includes a data processor and memory that are coupled to debug circuitry that generates debug messages including address translation trace messages. A memory management unit (MMU) includes a translation lookaside buffer (TLB) for ... | 08/02/2011 |
| 7984337 | Address translation trace message generation for debug A data processing system and method generates debug messages by permitting an external debug tool to have real-time trace functionality. A data processor executes a plurality of data processing instructions and uses a memory for information storage. Debug circuitry ... | 07/19/2011 |
| 7965130 | Low power charge pump and method of operation A charge pump and method for starting up a charge pump are provided. The charge pump comprises a plurality of charge pump cells and a start-up control circuit. Each charge pump cell has a clock terminal for receiving a delayed clock signal, an input terminal for rec... | 06/21/2011 |
| 7948301 | Charge pump with charge feedback and method of operation A charge pump charges a first capacitor to a predetermined input voltage using a first switch. The first switch is coupled to a first terminal of the first capacitor for coupling the first terminal to an input terminal that receives the predetermined input voltage. ... | 05/24/2011 |
| 7937573 | Metric for selective branch target buffer (BTB) allocation A method and data processing system allocates entries in a branch target buffer (BTB). Instructions are fetched from a plurality of instructions and one of the plurality of instructions is determined to be a branch instruction. A corresponding branch target address ... | 05/03/2011 |
| 7927989 | Method for forming a transistor having gate dielectric protection and structure A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to ... | 04/19/2011 |
| 7927934 | SOI semiconductor device with body contact and method thereof A method including providing a substrate and providing an insulating layer overlying the substrate is provided. The method further includes providing a body region comprising a body material overlying the insulating layer. The method further includes forming at leas... | 04/19/2011 |
| 7924108 | Oscillator amplifier with input clock detection and method therefor An oscillator circuit has a crystal oscillator amplifier having only two clock input terminals, one being an input terminal and the other being an output terminal. The input terminal allows a user of the integrated circuit to choose between connecting a first clock ... | 04/12/2011 |
| 7895422 | Selective postponement of branch target buffer (BTB) allocation A system and method provides branch target buffer (BTB) allocation. When a branch instruction is received, a branch target address that corresponds to the branch instruction is determined. A determination is made whether the branch target address is presently stored... | 02/22/2011 |
| 7873819 | Branch target buffer addressing in a data processor A branch target buffer (BTB) receives, from a processor, a current fetch group address which corresponds to a current fetch group including a plurality of instructions. In response to the current fetch group address resulting in a group hit in the BTB, the BTB provi... | 01/18/2011 |
| 7870400 | System having a memory voltage controller which varies an operating voltage of a memory and method therefor A system and method saves power in a system memory of a processing system. A peripheral, a processor, an arbiter and a system memory are coupled to a system communication bus for communicating via the system communication bus. In one form a voltage controller is cou... | 01/11/2011 |
| 7868877 | Touch panel detection circuitry and method of operation A touch panel detection circuit includes current limiting circuitry that has a first portion coupled between a first supply voltage terminal and a first input node and a second portion coupled between a second input node and a second supply voltage terminal. Program... | 01/11/2011 |
| 7859299 | Circuit for controlling data communication with synchronous storage circuitry and method of operation A method and circuit includes providing at least one conductor for receiving an input signal. A termination circuit and a clamp circuit are coupled to the at least one conductor. The termination circuit is enabled while the clamp circuit remains enabled. The clamp c... | 12/28/2010 |
| 7838363 | Method of forming a split gate non-volatile memory cell A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently for... | 11/23/2010 |
| 7834689 | MOS operational amplifier with current mirroring gain and method of operation An amplifier has an input stage coupled to a current mirror for providing a first control signal. A gain boosting stage has first and second sections, each having first and second inputs and an output. The first input of the first section is coupled to the input sta... | 11/16/2010 |
| 7823033 | Data processing with configurable registers A data processing system includes functional circuitry which performs at least one data processing function, a register file coupled to the functional circuitry and having a plurality of general purpose registers (GPRs) which are included as part of a user's program... | 10/26/2010 |
| 7820520 | Semiconductor device with capacitor and/or inductor and method of making An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal f... | 10/26/2010 |
| 7811889 | FinFET memory cell having a floating gate and method therefor A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure overlies the dielectric layer and has a first current electrode and a second... | 10/12/2010 |
| 7808286 | Circuitry in a driver circuit A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupl... | 10/05/2010 |
| 7807572 | Micropad formation for a semiconductor A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin r... | 10/05/2010 |
| 7804701 | Method of programming a memory having electrically programmable fuses An array of memory cells is arranged in a plurality of columns and rows, each of the memory cells including a programmable fuse connected to a predetermined bit line and in series with a select transistor. The select transistor has a first current electrode connecte... | 09/28/2010 |
| 7791367 | Driver with selectable output impedance An integrated circuit is configured to be in a calibration mode of operation to establish a desired output impedance of a driver circuit. A predetermined constant voltage is established at a circuit node within the integrated circuit. A calibration current is conduc... | 09/07/2010 |
| 7777522 | Clocked single power supply level shifter First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that differs from the first power supply domain. The data signal becomes ref... | 08/17/2010 |
| 7772584 | Laterally grown nanotubes and method of formation A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portio... | 08/10/2010 |
| 7741183 | Method of forming a gate dielectric A method of forming a semiconductor device includes providing a substrate for the semiconductor device. A base oxide layer is formed overlying the substrate by applying a rapid thermal oxidation (RTO) of the substrate in the presence of oxygen. A nitrogen-rich regio... | 06/22/2010 |
| 7734898 | System and method for specifying an immediate value in an instruction A data processing system uses a data processor instruction that forms an immediate value. The data processing instruction uses a first field as a portion of the immediate value. A second field of the data processing instruction determines a positional location of th... | 06/08/2010 |
| 7733711 | Circuit and method for optimizing memory sense amplifier timing A memory has an array of memory cells, a word line driver, a sense amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for coupling a storage portion to a bit line. The coupling transistors have an average threshold voltage and a maximu... | 06/08/2010 |
| 7727829 | Method of forming a semiconductor device having a removable sidewall spacer A semiconductor device is formed using a semiconductor substrate. A gate dielectric is formed over the semiconductor substrate. A gate electrode layer is formed over the gate dielectric. A patterned masking layer is formed over the gate electrode layer. A first regi... | 06/01/2010 |
| 7724603 | Method and circuit for preventing high voltage memory disturb A circuit and method reduces disturb in a memory array resulting from one of two supply voltages dropping below a predetermined value. Memory control logic is operated using a logic power domain. Higher voltages than that of the logic power domain are generated in r... | 05/25/2010 |
| 7717060 | Controlled electroless plating An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen ... | 05/18/2010 |
