Did You Know...
...that Charles Goodyear performed some of his experiments on rubber while in debtor's prison? He was there so often he referred to it as his "hotel". Chronically in debt because of poor business sense and ill health, Goodyear depended on the generosity of friends and family. Even after he unlocked the secret to vulcanizing rubber, he was unable to improve his financial situation. When he died, his estate was $200,000 in debt.
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| Number | Title | Issue Date |
| 7069482 | ROM error-correction control To determine the occurrence of an address for a defective memory, cell in a ROM, an error-correction control system includes a comparator that compares a set of incoming memory address signals with static signals provided by a laser-fuse array. The static signals re... | 06/27/2006 |
| 6981187 | Test mode for a self-refreshed SRAM with DRAM memory cells A self-refreshing SRAM with internal DRAM memory cells is provided with a test mode enable circuit for testing the real refresh time of the internal SRAM memory cells and for determining the maximum refresh capability of the internal DRAM memory cells. The self-refr... | 12/27/2005 |
| 6977860 | SRAM power reduction A SRAM uses a number of memory banks in a configuration that uses lower voltage swings on a differential internal data bus so that the internal data bus no longer uses single-ended VDD/VSS, HIGH-to-LOW, rail-to-rail voltage swing for a read mode of operation. This c... | 12/20/2005 |
| 6920528 | Smart memory A smart memory includes a memory array and one or more memory-intensive additional functions, all packaged in a standard memory package that has substantially the same fit and form as a standard integrated-circuit memory. One type of smart memory chip is a multi-med... | 07/19/2005 |
| 6856162 | AC/DC monitor system A combined AC/DC monitoring system simultaneously monitors an AC power supply and a DC power supply in a mobile unit. The monitoring system is electrically isolated from an AC input source through an AC isolation transformer. A microcontroller digitally provides var... | 02/15/2005 |
| 6771554 | Access delay test circuit for self-refreshing DRAM An enhanced arbitration and control subsystem for a self-refreshing DRAM has a normal mode of operation and a test mode of operation in which an internal refresh cycle is automatically performed prior to each external access cycle. A first gate is opened in a normal... | 08/03/2004 |
| 6757207 | Refresh miss detect circuit for self-refreshing DRAM A counter is incremented whenever an internal refresh is requested and a prior internal refresh request has not yet been completed. A refresh-request storage element such as a latch circuit, provides an output signal that is set upon receipt of an internal refresh r... | 06/29/2004 |
| 6741515 | DRAM with total self refresh and control circuit Internally refreshing one or more DRAM arrays without requiring additional external command signals. Scheduling of either refresh cycles and/or read/write access cycles uses an arbitration and selection circuit that receives a refresh request input signal from an in... | 05/25/2004 |
| 6735142 | Power-up control circuit with a power-saving mode of operation A power-up control circuit has three components including a normal power-supply voltage level detection section, a special command section for detecting a deep-sleep enable input signal, and an output driver section that logically combines the output signal of the n... | 05/11/2004 |
| 6721210 | Voltage boosting circuit for a low power semiconductor memory An improved voltage boosting circuit operates entirely from a single, common VCC voltage supply. An NMOS pass transistor has a gate input terminal to which is connected a gate boost capacitor and a PMOS precharge circuit. A drain terminal of the NMOS pass transistor... | 04/13/2004 |
| 6713855 | Dual die memory A double-sized chip assembly and method is provided for two back-to-back integrated-circuit chips which both have the same fabrication mask sets. An electrically-selectable bonding-pad connection option alternatively provides a standard, non-reversed, option NRO for... | 03/30/2004 |
| 6694448 | SRAM row redundancy A fuse-controlled, row-redundancy control system and method for a SRAM includes a multi-bit, defective-row storage array of static circuits that are programmed to store one of the address bits of a predetermined defective row of the SRAM and that includes... | 02/17/2004 |
| 6684805 | Rope loop connection system for yachts A connection system for Yachts comprising a lightweight rope loop (2) and a body part for connecting sheets, sails and blocks. A tensile connecting device comprises a high strength fiber rope with a first enlarged terminated end that is held captive in a ... | 02/03/2004 |
| 6681287 | Smart memory A smart memory includes a memory array and one or more memory-intensive additional functions, all packaged in a standard memory package that has substantially the same fit and form as a standard integrated-circuit memory. One type of smart memory chip is ... | 01/20/2004 |
| 6657880 | SRAM bit line architecture To alleviate the crosstalk between BL and BLN of the same column, the present invention provides vertical twisting for the bit line and the complementary bit line of a line pair connecting a column of memory bits to a sense amplifier. The BL and BLN run i... | 12/02/2003 |
| 6643216 | Asynchronous queuing circuit for DRAM external RAS accesses A method and queuing circuit are provided for storing asynchronous external RAS access requests and for executing corresponding RAS cycles. When no current external access RAS cycle is currently underway a first request latch or similar storage element is... | 11/04/2003 |
| 6593646 | Dual die memory A double-sized chip assembly and method is provided for two back-to-back integrated-circuit chips which both have the same fabrication mask sets. An electrically-selectable bonding-pad connection option alternatively provides a standard, non-reversed, opt... | 07/15/2003 |
| 6559678 | Node predisposition circuit A node predisposition circuit for driving an output node of an output buffer circuit is provided which is formed of a delay circuit, a pre-charge pull-up circuit, and a pre-charge pull-down circuit. The pre-charge pull-up and pull-down circuits are used f... | 05/06/2003 |
| 6508709 | Virtual distributed multimedia gaming method and system based on actual regulated casino games Virtual gaming is provided at a remote location on-site or off-site of the casino premises using live multimedia video or restricted pre-recorded video from autonomous randomly selected live casino games. The restricted pre-recorded video could be obtaine... | 01/21/2003 |
| 6493414 | Die information logic and protocol An on-chip parallel/load, serial-shift shift register stores information bits for one or more chip parameters. The bits are represented by fuses that are connected to respective input terminals of the shift register. When the chip is not in test mode (TM)... | 12/10/2002 |
| 6355980 | Dual die memory A double-sized chip assembly and method is provided for two back-to-back integrated-circuit chips which both have the same fabrication mask sets. An electrically-selectable bonding-pad connection option alternatively provides a standard, non-reversed, opt... | 03/12/2002 |
| 6295753 | Laser precision bore sight assembly A laser precision bore sight assembly and method aligns a laser beam along the longitudinal axis of a gun barrel. At the proximate end of an elongated bore shaft is rotatably mounted a compressible barrel insert with a continuous outer surface which resil... | 10/02/2001 |
| 6269105 | Use of features to represent independent bit streams or groups of bits in data transmission systems A method and apparatus for simultaneously communicating a first data stream along with a second data stream. A first carrier is modulated with a first data stream and a feature of the modulated first carrier is then imposed under the control of a second i... | 07/31/2001 |
| 6264778 | Reinforced sealing technique for an integrated circuit package One or more reinforcement pins are inserted between the lid and base of a sealed integrated-circuit package. The reinforcement pins reinforce a sealing layer between the lid and the base, particularly against shear forces exerted on the sealing layer betw... | 07/24/2001 |
| 6240029 | Memory column redundancy An incoming memory address signal is compared and matched with static signals provided by a fuse array that represents an address of a defective memory column that is being replaced by a redundant memory column in a memory chip. Each section of a memory i... | 05/29/2001 |
| 6233254 | Use of feature characteristics including times of occurrence to represent independent bit streams or groups of bits in data transmission systems A method and apparatus for simultaneously communicating a first data stream along with a second data stream. A first carrier is modulated with a first data stream and a feature of the modulated first carrier is then imposed under the control of a second i... | 05/15/2001 |
| 6228683 | High density leaded ball-grid array package A high density leaded ball-grid array package for packaging an integrated-circuit die includes a laminated substrate formed of a non-conductive layer sandwiched between first and second conductive trace patterns. A leadframe is directly attached onto the ... | 05/08/2001 |
| 6191483 | Package structure for low cost and ultra thin chip scale package Thin organic layers are laminated on both the top and bottom of a relatively thin ceramic layer to form a reliable thinner composite substrate for packaging a chip-scale flip-chip die in a thin package. A semiconductor die has a number of solder bump-moun... | 02/20/2001 |
| 6188721 | System and method for adaptive equalization of a waveform independent of absolute waveform peak value An improved adaptive equalizer providing the proper amount of equalization to restore the missing frequency components of a received and underequalized waveform. The invention'equalization gain or pulse counting feature can be set at various levels by dig... | 02/13/2001 |
| 6181172 | High voltage detect circuit with increased long term reliability A voltage detector circuit discriminates between a 13 volt Programming signal and a 6 volt signal without creating a field across the gate oxide of a sensing transistor in excess of 7.0 MegaV/cm. A PMOS transistor has a source terminal and a substrate ter... | 01/30/2001 |
| 6177726 | SiO2 wire bond insulation in semiconductor assemblies A semiconductor integrated circuit package is provided with insulated bonding wires. The semiconductor die is mounted to a base of either a leadframe or a grid-array package. A plurality of bonding wires are bonded between bonding pads on the semiconducto... | 01/23/2001 |
| 6167543 | Memory test mode circuit A memory-test-mode detection circuit for an integrated circuit uses one or more of the input pins of an integrated circuit to detect at least one non-standard signal level. To avoid false triggering several other non-standard logic levels can also be used... | 12/26/2000 |
| 6163209 | Demodulation of angle modulated carriers using a noncoherent reference A technique for demodulating a message signal from an angle modulated carrier signal. A noncoherent, independent, periodic reference is generated to have a predetermined phase characteristic and which is noncoherent with and independent of the angle modul... | 12/19/2000 |
| 6163226 | Current-controlled p-channel transistor-based ring oscillator A current-controlled oscillator (ICO) circuit including an all p-channel transistor based ring oscillator, a first current mirroring stage, and a second current mirroring stage. The all p-channel transistor based ring oscillator, p-channel transistors in ... | 12/19/2000 |
| 6148025 | System and method for compensating for baseline wander An improved invention providing a solution to a problem endemic to conventional adaptive equalizer systems, a problem known as baseline wander. The invention brings the baseline back down when it has drifted up due to baseline wander. The invention brings... | 11/14/2000 |
| 6087965 | Vehicle mileage meter and a GPS position tracking system A trip meter, such as a taximeter or a mileage meter for a commercial vehicle, such as a truck, are combined with an integral GPS receiver/computer which provides GPS position and time information. Odometer input pulses to the trip meter are accurately ca... | 07/11/2000 |
| 6083776 | Molded lead frame ball grid array A ball grid array (BGA) package configuration for packaging an integrated-circuit die includes a lead frame having a plurality of inwardly-extending bonding fingers and a centrally-located die-attach pad. The bonding fingers are disposed peripherally surr... | 07/04/2000 |
| 6069407 | BGA package using PCB and tape in a die-up configuration A die-up configuration includes a rigid circuit board with electrically conductive plated-through holes formed therethrough and an integrated-circuit die mounted to the upper surface of which a flexible insulated tape layer is fixed to the upper surface o... | 05/30/2000 |
| 6057177 | Reinforced leadframe to substrate attachment A method and apparatus for a reinforced leadframe to substrate attachment in a semiconductor assembly. In one embodiment, a printed circuit board having a plurality of electrically coupled electrical contact regions and wire bond areas formed thereon has ... | 05/02/2000 |
| 6047467 | Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microelectronics packages via conduction through the package leads A method for minimizing signal delays caused by mismatch in length of the inner leads of a package lead frame. This is accomplished by the provision of a unique conductive trace pattern formed preferably on the top surface or else on a lower surface of an... | 04/11/2000 |
