Bizarre Patents
User-operated amusement apparatus for kicking the user's buttocks
An apparatus including a user-operated and controlled apparatus for self-infliction of repetitive blows to the user's buttocks by a plurality of elongated arms bearing flexible extensions that rotate under the user's control.
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| Number | Title | Issue Date |
| 8185850 | Method of implementing a circuit design using control and data path information A method of implementing a circuit design is described. The method comprises specifying criteria for control and data path identification; generating a representation for the circuit design; analyzing the representation based upon the criteria for control and data p... | 05/22/2012 |
| 8183881 | Configuration memory as buffer memory for an integrated circuit Method and apparatus for using configuration memory for buffer memory is described. Drivers associated with a portion of the configuration memory are rendered incapable of creating a contentious state irrespective of information stored the portion of configuration m... | 05/22/2012 |
| 8180919 | Integrated circuit and method of employing a processor in an integrated circuit According to various embodiments of the present invention, an intelligent framer/mapper integrates the framer, mapper, and the controlling function of the host processor, implemented as either a soft processor or an embedded processor, into a single device, such as ... | 05/15/2012 |
| 8155907 | Methods of enabling functions of a design to be implemented in an integrated circuit device and a computer program product Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice... | 04/10/2012 |
| 8149612 | Memory array and method of implementing a memory array A memory array having a plurality of memory cells is disclosed, where each memory cell comprises a first inverter having a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the firs... | 04/03/2012 |
| 8146040 | Method of evaluating an architecture for an integrated circuit device A method of evaluating an architecture for an integrated circuit device is disclosed. The method comprises generating a library of primitives for a predetermined architecture; transforming an original dataflow program into an intermediate format; transforming the in... | 03/27/2012 |
| 8146036 | Circuit for and method of determining a process corner for a CMOS device A circuit for determining a process corner for a CMOS device of an integrated circuit is disclosed. The circuit comprises a CMOS monitoring circuit comprising an NMOS transistor and a PMOS transistor of the integrated circuit; reference circuit comprising elements f... | 03/27/2012 |
| 8145923 | Circuit for and method of minimizing power consumption in an integrated circuit device A method of minimizing power consumption in an integrated device is disclosed. The method comprises providing a plurality of circuit blocks having circuits for performing logic functions, wherein each circuit block consumes power in a static state; coupling one of a... | 03/27/2012 |
| 8139610 | Method for framing data for transmission over an encoded channel A serializer is provided to serialize combined synchronization information and data blocks for transmission over the high-speed channel. A gearbox combines synchronization information with data blocks to present to the serializer. A scrambler scrambles data blocks t... | 03/20/2012 |
| 8134813 | Method and apparatus to reduce footprint of ESD protection within an integrated circuit An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to... | 03/13/2012 |
| 8134418 | Varactor circuit and voltage-controlled oscillation A varactor circuit and voltage-controlled oscillation are described. The varactor circuit includes a first varactor, a second varactor, a third varactor, and a fourth varactor. A first source-drain node of the first varactor and a second source-drain node of the sec... | 03/13/2012 |
| 8130027 | Apparatus and method for the detection and compensation of integrated circuit performance variation An apparatus and method for the dynamic detection and compensation of performance variations within an integrated circuit (IC) is provided to detect performance variations within the IC at any stage of test or operation. An arbitrary reference signal is utilized in ... | 03/06/2012 |
| 8120075 | Semiconductor device with improved trenches A semiconductor device exhibiting enhanced carrier mobility within a channel region of the semiconductor device is disclosed. The semiconductor device includes a gate stack having first and second sidewall spacers, where the gate stack is implemented above the chann... | 02/21/2012 |
| 8117247 | Configurable arithmetic block and method of implementing arithmetic functions in a device having programmable logic A configurable arithmetic block in a device having programmable logic for implementing arithmetic functions is disclosed. The configurable arithmetic block comprises a plurality of input registers coupled to receive multiple bit words; an arithmetic function circuit... | 02/14/2012 |
| 8103919 | Circuit for and method of repairing defective memory A circuit for repairing defective memory of an integrated circuit is disclosed. The circuit includes blocks of memory; and interconnect elements providing data to each of the blocks of memory, where the interconnect elements enable coupling together the signals for ... | 01/24/2012 |
| 8102188 | Method of and system for implementing a circuit in a device having programmable logic A method of implementing a circuit in a device having programmable resources and a predetermined amount of available internal memory is disclosed. The method comprises configuring the programmable resources of the device with a circuit design; storing a first page o... | 01/24/2012 |
| 8099449 | Method of and circuit for generating a random number using a multiplier oscillation A method of generating a random number using a multiplier oscillation, the method comprising providing a multiplier circuit coupled to receive a first digital input and a second digital input, wherein the first digital input and the second digital input are asynchro... | 01/17/2012 |
| 8090755 | Phase accumulation A method for accumulation of information is described. The information is separated into first portions of MSBs and second portions of LSBs. The first and second portions are respectively input to a first adder and a second adder to provide first and second sums. Th... | 01/03/2012 |
| 8090335 | Method and apparatus for an adaptive step frequency calibration An open loop frequency calibration algorithm is employed whereby frequency counters are utilized to provide frequency information concerning the difference in frequency between a local oscillator and a reference signal prior to obtaining phase locked operation of a ... | 01/03/2012 |
| 8090037 | OFDM modulation using a shaping filter Reducing peak-to-average power ratio (“PAPR”) for modulation and demodulation is described. Complex sample values are obtained in a time domain for orthogonal frequency division multiplexed (“OFDM”) signaling. The complex sample values are transformed into a... | 01/03/2012 |
| 8086435 | Method for predicting simultaneous switching output (SSO) noise A method for the prediction of simultaneous switching output (SSO) noise that may be generated by one or more signal conduction paths within an electrical system. Electrical disturbance waveforms are first recorded for each signal conduction path that may be affecte... | 12/27/2011 |
| 8084297 | Method of implementing a capacitor in an integrated circuit A method of implementing a capacitor in an integrated circuit package is disclosed. The method comprises coupling the capacitor to a first surface of a substrate of the integrated circuit package; positioning an integrated circuit die over the capacitor, wherein the... | 12/27/2011 |
| 8079009 | Managing interrupt requests from IP cores A system and method of managing interrupt requests from IP cores within an integrated circuit design can include capturing environmental constraints within constraint files for the integrated circuit design (where the constraints can include information regarding a ... | 12/13/2011 |
| 8077219 | Integrated circuit having a circuit for and method of providing intensity correction for a video A method of providing intensity correction for a video is disclosed. The method may comprise evaluating a portion of a frame of the video; determining a difference in intensity of a current block of the frame with the corresponding block of the previous frame; corre... | 12/13/2011 |
| 8063656 | Method of enabling a circuit board analysis A method of enabling a circuit board analysis is disclosed. The method comprising removing a portion of the circuit board on a first side of the circuit board opposite a second side of the circuit board having an integrated circuit package; removing the circuit boar... | 11/22/2011 |
| 8062968 | Interposer for redistributing signals A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through ... | 11/22/2011 |
| 8058924 | Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, wh... | 11/15/2011 |
| 8015530 | Method of enabling the generation of reset signals in an integrated circuit A method of enabling the generation of reset signals in an integrated circuit is disclosed. The method comprises receiving information related to reset ports for a plurality of intellectual property cores in a design tool; providing an intellectual property core com... | 09/06/2011 |
| 8010590 | Configurable arithmetic block and a method of implementing a configurable arithmetic block in a device having programmable logic A configurable arithmetic block for implementing arithmetic functions in a device having programmable logic is described. The configurable arithmetic block comprises a first plurality of registers coupled to receive input data; a second plurality of registers couple... | 08/30/2011 |
| 8006021 | Processor local bus bridge for an embedded processor block core in an integrated circuit A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master proc... | 08/23/2011 |
| 8001171 | Pipeline FFT architecture for a programmable device A pipeline Fast Fourier Transform (“FFT”) architecture for a programmable device is described. A first Radix-2 butterfly stage is coupled to receive a first input, configured to provide a first output responsive thereto, and configured to truncate at least one L... | 08/16/2011 |
| 7998853 | Semiconductor device with through substrate vias Methods for making and testing a semiconductor device with through substrate vias are described. In some examples, a method of making a semiconductor device includes: forming through substrate vias (TSVs) in a substrate having an integrated circuit (IC) die, the sub... | 08/16/2011 |
| 7994631 | Substrate for an integrated circuit package and a method of forming a substrate A substrate for an integrated circuit package is disclosed. The substrate comprises a core comprising a first dielectric layer having a first thickness; conductive traces formed on the first dielectric layer for routing signals within the integrated circuit package,... | 08/09/2011 |
| 7994610 | Integrated capacitor with tartan cross section A capacitor in an IC has a first layer of conductive strips extending along a first direction (Z-direction). A first plurality of conductive strips in the first layer forms a portion a first node of the capacitor and alternates with a second plurality of conductive ... | 08/09/2011 |
| 7994609 | Shielding for integrated capacitors A capacitor in an integrated circuit (“IC”) includes a core capacitor portion having first conductive elements electrically connected to and forming a part of a first node of the capacitor formed in a first layer and second conductive elements electrically conne... | 08/09/2011 |
| 7984091 | Quadratic approximation for fast fourier transformation Interpolators for quadratic approximation for sinusoids are described. A sample source providing first order derivatives of sub-sampled sets of phase factor samples is used. A differentiator is coupled to receive the first order derivatives and configured to provide... | 07/19/2011 |
| 7979835 | Method of estimating resource requirements for a circuit design A method of estimating resource requirements for a circuit design is disclosed. The method comprises identifying intermediate circuit modules of a netlist associated with the circuit design; accessing a library of resource requirements for intermediate circuit modul... | 07/12/2011 |
| 7979827 | Device having programmable resources and a method of configuring a device having programmable resources A method of configuring a device having programmable logic is disclosed. The method comprises generating a netlist associated with a circuit design; coupling the netlist to the device having programmable logic; performing a re-targeting function using a circuit on t... | 07/12/2011 |
| 7970090 | Method and apparatus for a self-synchronizing system A self-synchronizing system that provides a master system component and a master clock source to provide a stable timing reference to the master system component. Timing information is then propagated throughout the system via encoded transmissions containing the ti... | 06/28/2011 |
| 7958394 | Method of verifying a triple module redundant system A method of verifying a triple module redundant circuit. The method comprises providing three circuits, each comprising a redundant circuit; coupling a feedback voter circuit at the output of each circuit of the three circuits, each feedback voter receiving the outp... | 06/07/2011 |
