Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Number | Title | Issue Date |
| 5317725 | Landmark data abstraction paradigm to diagnose data communication networks An expert system for diagnosing data communication networks. The expert system operates according to a landmark data abstraction paradigm, wherein landmarks are interpretations of network data. The landmarks are indicators of network problems. The expert ... | 05/31/1994 |
| 5313568 | Three dimensional computer graphics employing ray tracing to compute form factors in radiosity A method for rendering a three-dimensional image on a computer graphics display device involving the steps of providing a data base defining at least the geometry and reflectivity of light emitters and object in the scene and approximating surfaces of eac... | 05/17/1994 |
| 5306962 | Qualified non-overlapping clock generator to provide control lines with non-overlapping clock timing A clocking methodology for VLSI chips which uses global overlapping clocks, locally or remotely generated non-overlapping clocks, combined with pipeline control signals to generate signals which control the transfer gates of registers in a pipeline. The s... | 04/26/1994 |
| 5301269 | Window-relative dither circuit A circuit for performing window-relative dithering of intensity data comprises a programmable dither cell; circuitry for comparing dither values stored in the dither cell with selected parts of the intensity values and outputting an increment signal in ac... | 04/05/1994 |
| 5301156 | Configurable self-test for embedded RAMs A configurable self-test circuit for a RAM embedded in an integrated circuit chip comprises an incrementable address register, a configurable control circuit, a write register, a signature generator, and a scanpath. The address register stores the current... | 04/05/1994 |
| 5299158 | Memory device with multiple read ports A memory device having a plurality of read ports which can be dumped simultaneously without affecting the data stored in the memory cells of the memory device. The read ports of the memory device of the invention include dump circuits comprising a pair of... | 03/29/1994 |
| 5299298 | Accelerated shadow testing method for three dimensional graphics rendering system Shadow testing of a two dimensional projection of a three dimensional scene is accelerated by superimposing the projection with a plurality of scan areas, then examining points, and edges of objects, falling within each scan area. Points are identified as... | 03/29/1994 |
| 5296047 | Epitaxial silicon starting material A silicon starting material for fabricating integrated circuits is desrcibed that comprises a silicon wafer substrate material and a first epitaxial layer grown on the wafer substrate which eliminates stacking faults in the subsequent fabrication of a sem... | 03/22/1994 |
| 5297251 | Method and apparatus for pixel clipping source and destination windows in a graphics system A method of moving blocks of pixel data, including window-identifying data, from a source area to a destination area within a frame buffer in a computer graphics system comprises the steps of: reading a block of pixel data from the source area into a pixe... | 03/22/1994 |
| 5295245 | Data rotator for rotating pixel data in three dimensions A three-dimensional pixel cache for use in a computer graphics system comprises source, pattern, and destination tile caches and a barrel shift register, or rotator, that serves as an interface between the tile caches and a frame buffer. The rotator has t... | 03/15/1994 |
| 5287442 | Serpentine rendering of antialiased vectors in a computer graphics system Antialiased vectors, composed of a plurality of pixels along the vector minor axis for each major axis step, are rendered such that consecutively rendered pixels are always adjacent. For each major axis step, pixels are rendered along the minor axis in an... | 02/15/1994 |
| 5278949 | Polygon renderer which determines the coordinates of polygon edges to sub-pixel resolution in the X,Y and Z coordinates directions A polygon rendering circuit for a computer color graphics system comprising an edge stepper which steps along edges of an input polygon to determine the span of the polygon along each scan line intersected by the polygon. The coordinate values of the edge... | 01/11/1994 |
| 5274800 | Automatic signal configuration A system and method are disclosed for automatically configuring the interconnection of circuit boards in slots on the backplane of a computer. Some signal lines, such as bus grant and interrupt acknowledge signals, must be daisy-chained, or connected in s... | 12/28/1993 |
| 5257214 | Qualification of register file write enables using self-timed floating point exception flags A floating point processor in which floating point register file write enables are self-timed from the exception flags from the respective floating point processing units. This self-timing is achieved by forming the floating point processing units from se... | 10/26/1993 |
| 5251296 | Methods and apparatus for generating arbitrarily addressed, arbitrarily shaped tiles in computer graphics systems Methods and apparatus for rendering graphics primitives to display devices in a computer graphics frame buffer system are disclosed. The methods provide an array of addressable video random access memory (VRAM) chips associated to form the graphics frame ... | 10/05/1993 |
| 5233637 | System for generating an analog regulating voltage A system for generating an analog regulating voltage to be supplied to one or more circuit elements on an integrated circuit. The circuit elements have operational characteristics that are voltage dependent and the analog regulating voltage having the a p... | 08/03/1993 |
| 5233689 | Methods and apparatus for maximizing column address coherency for serial and random port accesses to a dual port RAM array Methods and apparatus for maximizing column address coherency for serial and parallel port accesses to a dual port frame buffer. Performance of the serial port of the frame buffer is greatly improved by separating the page boundaries in the horizontal dir... | 08/03/1993 |
| 5229853 | System for converting a video signal from a first format to a second format An apparatus for converting a video input signal representing an image from a first format to a prescribed second format. The apparatus comprises the following elements: a sync separator (30) for extracting a synchronization (sync) signal from the video i... | 07/20/1993 |
| 5229988 | System and method for distinguishing proxy replies of interconnecting devices from duplicate source address replies of non-interconnecting devices on a network System and method for distinguishing duplicate source address replies caused by interconnecting devices connected to a local area network and duplicate source address replies caused by non-interconnecting devices connected to the local area network. The p... | 07/20/1993 |
| 5224210 | Method and apparatus for graphics pipeline context switching in a multi-tasking windows system Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pi... | 06/29/1993 |
| 5222243 | Sorting apparatus having plurality of registers with associated multiplexers and comparators for concurrently sorting and storing incoming data according to magnitude Apparatus for receiving and automatically storing data words according to magnitude is provided. A self-sorting stack embodying the invention comprises a sorting device comprising means for simultaneously comparing the incoming data with the contents of e... | 06/22/1993 |
| 5222204 | Pixel interpolation in perspective space A method and apparatus for interpolating pixels to be displayed on a display screen so as to account for the nonlinearity of distance changes in the perspective projection of a 3-D object onto the display for corresponding linear distance changes in 3-D w... | 06/22/1993 |
| 5222205 | Method for generating addresses to textured graphics primitives stored in rip maps Methods for texture mapping graphics primitives in a graphics pipeline architecture system. The methods utilize rectangular box filters to down-sample original texture maps thereby optimizing aliasing and blurring when graphics primitives have a two-dimen... | 06/22/1993 |
| 5220650 | High speed method for rendering antialiased vectors A scan conversion algorithm for rendering antialiased vectors in a multi-processor graphics system comprises the following steps: providing signals to the processors indicative of scan lines the respective processors are responsible for, determining a fir... | 06/15/1993 |
| 5214680 | CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration The present invention is a time vernier providing fine timing control of an input signal having coarse timing edges. The time vernier comprises a receiving means for receiving a value representing a desired time delay to be added to the coarse timing edge... | 05/25/1993 |
| 5208490 | Functionally complete family of self-timed dynamic logic circuits A logic system uses novel mousetrap logic gates which implement novel vector logic. In a vector logic system, any number of valid vector logic states and one invalid vector logic state is defined by the logic signals on a set of logic paths. An invalid ve... | 05/04/1993 |
| 5198805 | Method and apparatus for monitoring a network and locating a node using signal strength calculations Disclosed is a system that monitors the signal strength of each transmission by a node on a LAN cable of a local area network and determines the location of the node sending the signal. This system has a monitor at each end of the LAN cable, with one of t... | 03/30/1993 |
| 5196741 | Recycling ramp interpolator A recycling ramp interpolator is described which can provide multiple measurements for a single input trigger signal by maintaining initial input waveform reference and interpolating multiple times before completely discharging. The interpolator reference... | 03/23/1993 |
| 5193148 | Method and apparatus for pixel clipping source and destination windows in a graphics system A method of moving blocks of pixel data, including window-identifying data, from a source area to a destination area within a frame buffer in a computer graphics system comprises the steps of: reading a block of pixel data from the source area into a pixe... | 03/09/1993 |
| 5185856 | Arithmetic and logic processing unit for computer graphics system Pixel arithmetic and logical units for rendering pixels in graphics systems. Circuits for performing arithmetic operations on raster scan data are provided. The circuits comprise opcode registers for selecting an arithmetic function which transforms pixel... | 02/09/1993 |
| 5185735 | Lan noise monitor An apparatus and method for monitoring voltage on a LAN cable on which data is conveyed by negative-going pulses. Positive voltage on the LAN cable is interpreted as noise. Positive voltage is detected by, for example, comparing the voltage on the LAN cab... | 02/09/1993 |
| 5177595 | Microchip with electrical element in sealed cavity A method of producing a microchip having at least a portion of an electrical circuit element contained within a hermetically sealed enclosure comprising the steps of: forming a cavity in a first substrate assembly which has a cavity opening at a first sur... | 01/05/1993 |
| 5170152 | Luminance balanced encoder A color encoder for reducing visible artifacts even when the values of the respective color signals are truncated during encoding. Since the human eye is most sensitive to luminance variations in the displayed image, luminance errors (and hence visible ar... | 12/08/1992 |
| 5139918 | Photoresist system and photoetching process employing an I-line peak light source The disclosed photoresist process employs an i-line peak containing light source, such as that of the mercury spectrum, in conjunction with a dye capable of both absorbing i-line light and withstanding subsequent those baking procedures employed in produc... | 08/18/1992 |
| 5140174 | Symmetric edge true/complement buffer/inverter and method therefor The present invention is directed to a buffer/inverter which generates symmetric and complementary output signals from a single input signal. The device employs four inverters having similar switching speeds. The true output signal is generated by passing... | 08/18/1992 |
| 5133049 | Accelerated decomposition of small polygons into trapezoids A method and device for improving the processing performance of a transform engine by off-loading the processing of those input polygons which have no more than a predetermined number of edges and decomposing such polygons into trapezoids which can be ren... | 07/21/1992 |
| 5132558 | Recycling ramp interpolator A recycling ramp interpolator is described which can provide multiple measurements for a single input trigger signal by maintaining initial input waveform reference and interpolating multiple times before completely discharging. The interpolator reference... | 07/21/1992 |
| 5129794 | Pump apparatus A pump apparatus comprising an enclosure for holding a volume of fluid; an intake one-way valve for enabling intake of fluid into the enclosure; a discharge one-way valve for enabling discharge of fluid from the enclosure; a diaphragm for cyclically defle... | 07/14/1992 |
| 5130896 | Apparatus for electromagnetic interference containment for printed circuit board connectors A printed circuit board for mounting in a housing, having a mounted connector for making connections with the circuit board through the housing includes a layer formed from electrically insulating material and a conductive structure formed on such layer w... | 07/14/1992 |
| 5129051 | Decomposition of arbitrary polygons into trapezoids A technique for decomposing any simple or complex arbitrary polygon into a trapezoid having at least one edge parallel to the scan direction for more efficient scan conversion by rasterization circuitry. An input polygon is split into "slabs", which are a... | 07/07/1992 |
