Keagy; Rose Alyssa - US Patent Attorneys and Agents

Attorney: Keagy; Rose Alyssa

Number of patents: 221
Last date: May 22, 2012

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Number	Title	Issue Date
8184474	Asymmetric SRAM cell with split transistors on the strong side An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary NMOS driver or PMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. An integrated circuit containing an SRAM cell array in w...	05/22/2012
8179715	8T SRAM cell with four load transistors An integrated circuit containing SRAM cells with auxiliary load transistors on each data node. The integrated circuit also contains circuitry so that auxiliary load transistors in addressed SRAM cells may be biased independently of half-addressed cells. A process of...	05/15/2012
8178915	Unitary floating-gate electrode with both N-type and P-type gates An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-...	05/15/2012
8174914	Method and structure for SRAM Vmin/Vmax measurement A parametric test circuit is disclosed (FIG. 8B). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor (206) has a current path connected between the true terminal and a first access terminal (...	05/08/2012
8174884	Low power, single poly EEPROM cell with voltage divider An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIGS. 7 and 8) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (806) coupled to receive...	05/08/2012
8170858	Characterization and modeling of ferroelectric capacitors Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. ...	05/01/2012
8164945	8T SRAM cell with two single sided ports A dual port SRAM cell includes an auxiliary driver transistor on each data node. The SRAM cell is capable of single sided write to each data node. The auxiliary driver transistors in addressed cells may be biased independently of half-addressed cells. During write a...	04/24/2012
8159863	6T SRAM cell with single sided write An SRAM cell containing an auxiliary driver transistor is configured for a single sided write operation. The auxiliary driver transistor may be added to a 5-transistor single-sided-write SRAM cell or to a 7-transistor single-sided-write SRAM cell. The SRAM cell may ...	04/17/2012
8154938	Memory array power domain partitioning An integrated circuit containing a nonvolatile memory circuit which contains memory segments and sense amplifier banks individually powered by a power decoder circuit. A method of accessing a portion of a powered-down memory. ...	04/10/2012
8139431	Structure and methods for measuring margins in an SRAM bit Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, methods for measuring the read margin, write margin, and stability...	03/20/2012
8125830	Area-efficient electrically erasable programmable memory cell Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of t...	02/28/2012
8112400	Method for collecting data from semiconductor equipment A method for collecting data from semiconductor equipment includes selecting a plurality of data values to request from semiconductor equipment and assigning each of the data values to a chamber. Each chamber is associated with an engine that processes the data valu...	02/07/2012
8110855	Offset geometries for area reduction in memory arrays An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding an across cell border design rule violation between the adjacent simila...	02/07/2012
8085580	System for bitcell and column testing in SRAM A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read. ...	12/27/2011
8071430	Stress buffer layer for ferroelectric random access memory An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes provid...	12/06/2011
8067795	Single poly EEPROM without separate control gate nor erase regions A single-poly EEPROM memory device comprises source and drain regions in a semiconductor body, a floating gate overlying a portion of the source and drain regions, which defines a source-to-floating gate capacitance and a drain-to-floating gate capacitance, wherein ...	11/29/2011
8067792	Memory device with memory cell including MuGFET and FIN capacitor One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate ...	11/29/2011
8067279	Application of different isolation schemes for logic and embedded memory The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relat...	11/29/2011
8064279	Structure and method for screening SRAMS An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also provides different wordline and array voltages during a portion of the SRAM bit screening test. A method ...	11/22/2011
8064275	Local sensing and feedback for an SRAM array An integrated circuit having an SRAM array includes SRAM cells arranged in rows and columns, and a global read circuit connected to globally read SRAM cells corresponding to accessed rows and columns of the SRAM array. The SRAM array also includes a separate, local ...	11/22/2011
8064271	Static random access memory device having bit line voltage control for retain till accessed mode and method of operating the same A static random-access memory (SRAM) and a method of controlling bit line voltage. In one embodiment, the SRAM includes: (1) an array of SRAM cells organized in rows and columns, (2) bit lines associated with the columns, (3) a high voltage power supply configured t...	11/22/2011
8058677	Stress buffer layer for ferroelectric random access memory An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes provid...	11/15/2011
8018780	Temperature dependent back-bias for a memory array The present invention provides a thermostatic bias controller for use with a memory array. The thermostatic bias controller includes a temperature sensing circuit configured to sense a temperature associated with the memory array. The thermostatic bias controller al...	09/13/2011
8012842	Method for fabricating isolated integrated semiconductor structures An integrated semiconductor structure that has first and second bipolar transistor structures. The first bipolar transistor structure has a doped tank region in contact with a doped tank region located underneath a contacting sinker. The second bipolar transistor st...	09/06/2011
7994073	Low stress sacrificial cap layer A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film. Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 an...	08/09/2011
7986566	SRAM cell with read buffer controlled for low leakage current A functional memory of the integrated circuit includes row and column periphery units and an array of memory cells having a core storage element and a read buffer. The functional memory further includes a read buffer supply line that is connected to the read buffer,...	07/26/2011
7985990	Transistor layout for manufacturing process control A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) o...	07/26/2011
7985603	Ferroelectric capacitor manufacturing process A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, whe...	07/26/2011
7984319	Memory bus shared system The invention reduces the pin terminal number of a controller that in parallel or simultaneously accesses a synchronous memory and an asynchronous memory. When a column address is latched to an SDRAM, immediately after that, access to FLASH is started, and a shared ...	07/19/2011
7983071	Dual node access storage cell having buffer circuits An integrated circuit includes an array of memory cells, each including a core storage element with first and second complementary storage nodes and first and second cell pass transistors coupled to the first and second storage nodes, respectively. In the cell, a fi...	07/19/2011
7968974	Scribe seal connection A feedthrough in an IC scribe seal is disclosed. The feedthrough is structured to maintain isolation of components in the IC from mechanical damage and chemical impurities introduced during fabrication and assembly operations. A conductive structure penetrates the s...	06/28/2011
7957178	Storage cell having buffer circuit for driving the bitline An integrated circuit includes a memory array including a plurality of memory cells, the memory cells include a core storage element having at least a first storage node (S) and a complementary second storage node (S-bar), and a first pass gate coupled to the first ...	06/07/2011
7943499	FUSI integration method using SOG as a sacrificial planarization layer A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG ...	05/17/2011
7936589	Adaptive voltage control for SRAM The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM for both Vtrip and SNM to reduce power while maintaining functionality and performance, based on modeling a...	05/03/2011
7933138	F-RAM device with current mirror sense amp A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing...	04/26/2011
7920404	Ferroelectric memory devices with partitioned platelines One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in rows and columns. A row of ferroelectric memory cells includes a common wordline that allows access to th...	04/05/2011
7919368	Area-efficient electrically erasable programmable memory cell Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of t...	04/05/2011
7907456	Memory having circuitry controlling the voltage differential between the word line and array supply voltage An integrated circuit (IC) includes at least one memory array having a plurality of memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns ...	03/15/2011
7902055	Method of manufacturing a dual metal Schottky diode An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode ...	03/08/2011
7898837	F-SRAM power-off operation A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each read oper...	03/01/2011

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Attorney: Keagy; Rose Alyssa