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| Number | Title | Issue Date |
| 8024678 | Interfacing with a dynamically configurable arithmetic unit An interface to a dynamically configurable arithmetic unit can include data alignment modules, where each data alignment module receives input variables being associated with one or more arithmetic expressions. The interface can include multiplexers coupled to the d... | 09/20/2011 |
| 7765508 | Method and system for generating multiple implementation views of an IC design A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be generated. In one embodiment an array of rows and columns is formed on... | 07/27/2010 |
| 7757194 | Method and system for generating implementation files from a high level specification A method and system for generating implementation files from a high level specification are described. In one example, a method for creating a package file for an integrated circuit is described. First, a grid is formed having a plurality of blocks. A height and a w... | 07/13/2010 |
| 7580924 | Method and system for collection, analysis, and display of semiconductor manufacturing information A server system for receiving and processing manufacturing data from a plurality of semi-conductor manufacturers is disclosed. The server system includes: a file capture module for receiving the manufacturing data from the plurality of semi-conductor manufacturers; ... | 08/25/2009 |
| 7571395 | Generation of a circuit design from a command language specification of blocks in matrix form Generation of a circuit design using a command language. The various approaches include generating in a memory arrangement respective instances of design blocks in response to user-entered commands that specify creation of the instances. Matrix-relative positions of... | 08/04/2009 |
| 7567997 | Applications of cascading DSP slices In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for config... | 07/28/2009 |
| 7557610 | Columnar floorplan An FPGA is laid out as a plurality of repeatable tiles, wherein the tiles are disposed in columns that extend from one side of the die to another side of the die, and wherein each column includes tiles primarily of one type. Because substantially all die area of a c... | 07/07/2009 |
| 7523434 | Interfacing with a dynamically configurable arithmetic unit An exemplary embodiment includes a method that receives a plurality of mathematical expressions having a plurality of input variables. The mathematical expressions can then be parsed, checked for proper syntax and one or more abstract syntax trees can be formed. Nex... | 04/21/2009 |
| 7506015 | Generation of a remainder from division of a first polynomial by a second polynomial Generation a remainder from a division of a first polynomial by a second polynomial having a variable width. One or more embodiments include a first sub-circuit, a first adder, a second sub-circuit, and a second adder. The first sub-circuit is adapted to generate a ... | 03/17/2009 |
| 7505512 | Method and apparatus for combining statistical eye channel compliance methods with linear continuous-time equalization A method and apparatus for combining statistical eye channel compliance methods with linear continuous-time equalization. A set of equalizer parameters is processed with measured channel parameters to create a set of modified parameters that are then used with a sta... | 03/17/2009 |
| 7499513 | Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data out... | 03/03/2009 |
| 7480789 | Virtual file system interface to configuration data of a PLD Methods and apparatus are described for providing access to data in a programmable logic device (PLD). A hierarchy of directories and files are maintained in a virtual file system, which is registered with an operating system. The directories and files are associate... | 01/20/2009 |
| 7380106 | Method and system for transferring data between a register in a processor and a point-to-point communication link A method and a system for transferring data between a register in a processor and a point-to-point communications link. More specifically, blocking and non-blocking methods are described to get and put data between a general purpose register of a soft or hard core p... | 05/27/2008 |
| 7349488 | Frequency shift keying signaling for integrated circuits The present invention relates to a system for communicating between two integrated circuits (ICs) or within an IC. The ICs are either on the same circuit boards or on different circuit boards with a common backplane. A first integrated circuit has transmitter circui... | 03/25/2008 |
| 7346794 | Method and apparatus for providing clocking phase alignment in a transceiver system A method and apparatus for providing clock phase alignment in a transceiver system are disclosed. Circuits are provided for providing clock phase alignment to adjust and align the phase between clock domain boundaries and for maintaining alignment of multiple output... | 03/18/2008 |
| 7346481 | Hardware co-simulation breakpoints in a high-level modeling system Various approaches for controlling simulation of an electronic system are disclosed. In one approach, at least one breakpoint block is instantiated in a high-level design. The breakpoint block has an associated breakpoint condition driven by at least one signal of t... | 03/18/2008 |
| 7334209 | Method and system for generating multiple implementation views of an IC design A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be generated. In one embodiment an array of rows and columns is formed on... | 02/19/2008 |
| 7315220 | Voltage controlled oscillator A voltage controlled oscillator (VCO) having a single stage ring-oscillator having both coarse and fine control of the frequency of oscillation is described. In an embodiment the VCO may include a first n-channel latch having a first output and a second output; a fi... | 01/01/2008 |
| 7314174 | Method and system for configuring an integrated circuit A system for programming configuration memory cells in an integrated circuit. The system includes: a set of data registers, wherein a member of the set has a temporary storage for a fixed number of configuration bits; and a plurality of rows, each row has a pluralit... | 01/01/2008 |
| 7284227 | Method and system for generating implementation files from a high level specification A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be generated. In one embodiment an array of rows and columns is formed on... | 10/16/2007 |
| 7284225 | Embedding a hardware object in an application system Various approaches for interfacing an application-independent hardware object with an application system are disclosed. The various approaches involve instantiating a first object that contains at least one configuration parameter. The configuration parameter specif... | 10/16/2007 |
| 7251168 | Interface for access to non-volatile memory on an integrated circuit An integrated circuit (IC) includes volatile memories, at least one non-volatile memory, at least one control circuit, and a configurable logic array. Each volatile memory has an associated interface including a respective first input and a respective second input. ... | 07/31/2007 |
| 7227378 | Reconfiguration of a programmable logic device using internal control A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified f... | 06/05/2007 |
| 7227375 | DAC based driver with selectable pre-emphasis signal levels A Transmit line driver with selectable pre-emphasis and driver signal magnitudes comprises a primary current driver for setting a primary current level and a pre-emphasis current driver that provides an additional amount of current that is superimposed with or added... | 06/05/2007 |
| 7187200 | Columnar architecture An integrated circuit (IC) is disclosed having circuitry arranged in a plurality of columns. A column in the IC is essentially a series of aligned circuit elements of the same type that extends from a first edge of the IC to a second edge. In addition there may be a... | 03/06/2007 |
| 7184466 | Radio frequency data conveyance system including configurable integrated circuits A data conveyance integrated system that can be utilized in a base station and/or end user devices in a wireless communication system. The integrated system includes first and second integrated circuits (ICs). The first IC includes a first serial-deserial (SERDES) m... | 02/27/2007 |
| 7161849 | First-in, first-out buffer system in an integrated circuit An integrated circuit having an embedded first-in, first-out (“FIFO”) memory system uses an embedded block random access memory (“BRAM”). Counters operate in both the read and write clock domains. A binary adder adds a first selected offset value and to a fi... | 01/09/2007 |
| 7161995 | Method and apparatus for Viterbi synchronization Method and apparatus are described for determining when a convolution decoder is out of synchronization. Normalizations from a convolutional decoder are counted to provide a normalization count, and errors from the convolutional decoder are counted to provide an err... | 01/09/2007 |
| 7149994 | Integrated clock and input output placer A method (200) of placing inputs, outputs, and clocks in a circuit design can include assigning (205) initial locations to inputs and outputs of the circuit design, selecting (210) at least one component type for the circuit design, and generati... | 12/12/2006 |
| 7149993 | Method, system, and apparatus for incremental design in programmable logic devices using floorplanning A method of designing a programmable logic device can include receiving a modification to a programmable logic device that has been floorplanned. Modules of the programmable logic device that have been changed by the modification can be identified. The changed modul... | 12/12/2006 |
| 7148758 | Integrated circuit with digitally controlled phase-locked loop An integrated circuit (“IC”) includes a phase-locked loop (“PLL”) with a controllable oscillator embedded in the integrated circuit. A phase-lock circuit provides a lock control signal to the controllable oscillator; and a digital-to-analog converter (“DAC... | 12/12/2006 |
| 7146590 | Congestion estimation for programmable logic devices A method of estimating congestion for a programmable logic device can include calculating a number of fan-in paths for each resource in the programmable logic device and calculating a number of fan-out paths for each resource in the programmable logic device. For ea... | 12/05/2006 |
| 7143369 | Design partitioning for co-stimulation Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. Groups of HDL components are associated with different co-simulation engines. The high-level components of the design are simulated in a high-l... | 11/28/2006 |
| 7142008 | Method and apparatus for clock division on a programmable logic device According to one example embodiment, a complex, programmable logic device (CPLD-type) has logic blocks and Input/Output (I/O) pads interconnected via a programmable interconnect array. A dedicated logic block is directly coupled to I/O pads, which provides external ... | 11/28/2006 |
| 7142033 | Differential clocking scheme in an integrated circuit having digital multiplexers A system for distributing a small signal differential signal to a circuit element. The system includes: a first converter configured to convert a first small signal differential signal to a first two phase full CMOS differential signal for input into the differentia... | 11/28/2006 |
| 7142557 | Programmable logic device for wireless local area network Method and apparatus for a wireless local area network programmable logic device is described. More particularly, a field programmable gate array (FPGA) is coupled to memory having programming instructions for configuring the FPGA with a medium access layer selected... | 11/28/2006 |
| 7143295 | Methods and circuits for dedicating a programmable logic device for use with specific designs Disclosed are methods and circuits that enable PLD vendors to dedicate PLDs for use with one or more specified designs. The PLD is programmed to store an indicator related to a specific design, for example, a hash function of the design, and to compare an indicator ... | 11/28/2006 |
| 7143376 | Method and apparatus for design verification with equivalency check Method and apparatus for design verification with equivalency checking is described. More particularly, an integrated circuit design for a device having programmable logic is obtained, and a test case design having one or more test patterns is obtained to test the i... | 11/28/2006 |
| 7138811 | Seals used for testing on an integrated circuit tester A system for reducing condensation during testing of an integrated circuit is disclosed. An exemplary embodiment includes two seals which close both ends of an enclosed channel formed when the load board is secured to the device tester. Clean dry air with a pressure... | 11/21/2006 |
| 7138815 | Power distribution system built-in self test using on-chip data converter A packaged semiconductor device uses built-in self test to characterize voltage between points within the semiconductor die during a current discontinuity generated in the semiconductor die. The semiconductor die is operated to generate a current discontinuity, or s... | 11/21/2006 |
