Did You Know...
...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8171211 | Method and system for minimizing impact of refresh operations on volatile memory performance A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly sch... | 05/01/2012 |
| 8165203 | Line-based video rate control A method for line-based video rate control is provided. The line based video rate control method includes system feedback to change system operating parameters, including on a packet-by-packet basis and also on a line-by-line basis. Also provided is a method for lin... | 04/24/2012 |
| 8159888 | Recalibration systems and techniques for electronic memory applications A memory circuit includes a delay module receiving a strobe signal and producing a delayed strobe signal therefrom. The memory circuit also includes a calibration module that initiates recalibration of the delay module when the calibration module discerns that the d... | 04/17/2012 |
| 8154900 | Method and apparatus for reducing power consumption in a content addressable memory Power consumption in a Content Addressable Memory (CAM) circuit is reduced by use of a CAM circuit. According to one embodiment of the CAM circuit, the CAM circuit includes a plurality of match lines and match line restoration circuitry. The match line restoration c... | 04/10/2012 |
| 8151266 | Operating system fast run command A fast sub-process is provided in an operating system for a digital signal processor (DSP). The fast sub-process executes a sub-process without a kernel first determining whether the sub-process resides in an internal memory, as long as certain conditions have been ... | 04/03/2012 |
| 8145883 | Preloading instructions from an instruction set other than a currently executing instruction set A preload instruction in a first instruction set is executed at a processor. The preload instruction causes the processor to preload one or more instructions into an instruction cache. The pre-loaded instructions are pre-decoded according to a second instruction set... | 03/27/2012 |
| 8145874 | System and method of data forwarding within an execution unit In an embodiment, a method is disclosed that includes, comparing, during a write back stage at an execution unit, a write identifier associated with a result to be written to a register file from execution of a first instruction to a read identifier associated with ... | 03/27/2012 |
| 8144658 | Method and apparatus for mitigating interference in a wireless communication system Techniques to mitigate inter-cell interference using joint time and frequency division are described. A frequency band is divided into multiple non-overlapping frequency subbands. The transmission timeline is divided into Tin and Tout time inte... | 03/27/2012 |
| 8144572 | Detection and mitigation of interference and jammers in an OFDM system The present invention provides a method and apparatus for detecting interference in a wireless communications system. The invention compares the receiver FFT output of a received signal against known sequences such as the packet synchronization sequence, frame synch... | 03/27/2012 |
| 8140823 | Multithreaded processor with lock indicator Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking... | 03/20/2012 |
| 8127184 | System and method including built-in self test (BIST) circuit to test cache memory A resizable cache memory and a system including a Built-In Self Test (BIST) circuit configured to test a cache memory are disclosed. The system further includes a non-volatile storage device including an E-fuse array to store one or more indicators. Each indicator i... | 02/28/2012 |
| 8127117 | Method and system to combine corresponding half word units from multiple register units within a microprocessor A method and system to combine corresponding half word units from multiple register units within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to combine predetermined dispa... | 02/28/2012 |
| 8127114 | System and method for executing instructions prior to an execution stage in a processor A method of processing a plurality of instructions in multiple pipeline stages within a pipeline processor is disclosed. The method partially or wholly executes a stalled instruction in a pipeline stage that has a function other than instruction execution prior to t... | 02/28/2012 |
| 8122231 | Software selectable adjustment of SIMD parallelism Selective power control of one or more processing elements matches a degree of parallelism to requirements of a task performed in a highly parallel programmable data processor. For example, when program operations require less than the full width of the data path, a... | 02/21/2012 |
| 8122187 | Refreshing dynamic volatile memory A memory system, and process for refreshing the memory, is disclosed. The memory system includes memory, a temperature sensor configured to measure the temperature of the memory, and a memory controller configured to refresh the memory at a refresh rate, the refresh... | 02/21/2012 |
| 8117420 | Buffer management structure with selective flush A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transa... | 02/14/2012 |
| 8116201 | Routing in a mesh network An apparatus includes a processing system configured to establish a link with any one of a plurality of access points in a mesh network, each of the access points providing the apparatus with a different data path through the mesh network. The processing system is f... | 02/14/2012 |
| 8108563 | Auxiliary writes over address channel A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the ... | 01/31/2012 |
| 8107492 | Cooperative writes over the address channel of a bus A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the ... | 01/31/2012 |
| 8102925 | Low peak-to-average ratio preamble, and associated method, for packet radio communication system Apparatus, and an associated method, for facilitating communications is a packet radio communication system, such as an IEEE 802.15.3a-compliant communication system. A deterministic sequence is used as a channel estimation sequence. The channel estimation sequence ... | 01/24/2012 |
| 8099448 | Arithmetic logic and shifting device for use in a processor An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectiv... | 01/17/2012 |
| 8098540 | Dynamic power saving memory architecture A memory includes multiple interface ports. The memory also includes at least two sub-arrays each having an instance of all of the bit lines of the memory and a portion of the word lines of the memory. The memory has a common decoder coupled to the sub-arrays and co... | 01/17/2012 |
| 8098539 | Hybrid single and dual channel DDR interface scheme by interleaving address/control signals during dual channel operation A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a single address/control bus. The memory controller couples to each of ... | 01/17/2012 |
| 8082428 | Methods and system for resolving simultaneous predicted branch instructions A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and ... | 12/20/2011 |
| 8082287 | Pre-saturating fixed-point multiplier A pre-saturating multiplier inspects the operands to a multiply operation prior to performing any multiplication. If the operands will cause an overflow requiring saturation, the multiplier outputs the saturated value without multiplying the original operands. In on... | 12/20/2011 |
| 8081691 | Detection of interferers using divergence of signal quality estimates A method, system, and computer-readable medium for detecting an interferer in a wireless communication system are provided. The method includes receiving a signal having P tones, each of the P tones being associated with a frequency, determining a first signal quali... | 12/20/2011 |
| 8078803 | Apparatus and methods to reduce castouts in a multi-level cache hierarchy Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next lev... | 12/13/2011 |
| 8063664 | Distributed supply current switch circuits for enabling individual power domains An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supp... | 11/22/2011 |
| 8060701 | Apparatus and methods for low-complexity instruction prefetch system When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction c... | 11/15/2011 |
| 8028143 | Method and apparatus for transmitting memory pre-fetch commands on a bus A processing system and method is disclosed wherein a processor may be configured to predict an address of memory from which data will be needed, transmit to a memory controller a pre-fetch command for the data at the predicted address of the memory, and transmit to... | 09/27/2011 |
| 8023988 | Power control for a channel with multiple formats in a communication system Techniques to more efficiently control the transmit power for a data transmission that uses a number of formats (e.g., rates, transport formats). Different formats for a given data channel (e.g., transport channel) may require different target SNIRs to achieved a pa... | 09/20/2011 |
| 8014277 | Restricting time slots for mesh networks Systems and methods are described that facilitate controlling transmission/reception time slots in a wireless multi-hop ad hoc network. A node, such as an access terminal or an access point, may select an identifier that corresponds to specific time slots during whi... | 09/06/2011 |
| 8008961 | Adaptive clock generators, systems, and methods Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock ... | 08/30/2011 |
| 7996695 | Circuits and methods for sleep state leakage current reduction A circuit for reducing sleep state current leakage is described. The circuit includes a hardware unit selected from at least one of a latch, a flip-flop, a comparator, a multiplexer, or an adder. The hardware unit includes a first node. The hardware unit further inc... | 08/09/2011 |
| 7996616 | Apparatus and methods to reduce castouts in a multi-level cache hierarchy Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next lev... | 08/09/2011 |
| 7992062 | Logic device and method supporting scan test A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data ... | 08/02/2011 |
| 7986165 | Voltage level shifter with dynamic circuit structure having discharge delay tracking An apparatus is disclosed. In a particular embodiment, the apparatus includes a a dynamic circuit structure that includes a dynamic node coupling a precharge circuit, a discharge circuit, and a gated keeper circuit. The gated keeper circuit is enabled by a signal fr... | 07/26/2011 |
| 7984281 | Shared interrupt controller for a multi-threaded processor A multi-threaded processor is disclosed that includes a sequencer adapted to provide instructions associated with one or more threads of a multi-threaded processor. The sequencer includes an interrupt controller adapted to receive one or more interrupts and to selec... | 07/19/2011 |
| 7984279 | System and method for using a working global history register A method of processing branch history information is disclosed. The method retrieves branch instructions from an instruction cache and executes the branch instructions in a plurality of pipeline stages. The method verifies that a branch instruction has been identifi... | 07/19/2011 |
| 7984202 | Device directed memory barriers Efficient techniques for controlling synchronization of bus transactions to improve performance and reduce power requirements in a shared memory system are described. Interconnect arrangements in complex processing systems are also described that provide efficient d... | 07/19/2011 |
