Kalson; Seth Z. - US Patent Attorneys and Agents

Attorney: Kalson; Seth Z.

Number of patents: 86
Last date: December 08, 2009

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Number	Title	Issue Date
7629830	Voltage level shifter A voltage level shifter circuit, comprising diodes to provide a voltage buffer to reduce output voltage swings, and edge detection circuits to momentarily turn on pull-up pMOSFETs so as to speed up the voltage level shifting at input signal transitions and to mitiga...	12/08/2009
7621536	Disc catching device A disc catching device for catching a thrown disc, having a canopy structure, a basket structure, an assembly coupled to the canopy structure and the basket structure, and a pole to which the canopy structure and the basket structure may be attached. The assembly ma...	11/24/2009
7620833	Power saving for isochronous data streams in a computer system For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether...	11/17/2009
7620134	Circuit to syncrhonize the phase of a distributed clock signal with a received clock signal A circuit to synchronize the phase of a distributed clock signal to a received clock signal. Embodiments include a control loop comprising a phase interpolator, a clock distribution network, and a data receiver. The clock distribution network provides a sampling clo...	11/17/2009
7604875	Mitigation of artifacts in nuclear magnetic resonance imaging with magnetic susceptibility modified materials Materials suitable for medical and dental implants with magnetic susceptibility matched to surrounding environment to reduce artifacts in nuclear magnetic resonance imaging. Paramagnetic and diamagnetic materials may be added to ceramics and polymer resins to adjust...	10/20/2009
7540929	Metallic glass alloys of palladium, copper, cobalt, and phosphorus Metallic glass alloys of palladium, copper, cobalt, and phosphorus, that are bulk-solidifying having an amorphous structure. Other embodiments are described and claimed. ...	06/02/2009
7535689	Reducing input capacitance of high speed integrated circuits An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity is formed underneath the pad. ...	05/19/2009
7511469	Phase measurement device using inphase and quadrature components for phase estimation A phasemeter for estimating the phase of a signal. For multi-tone signals, multiple phase estimates may be provided. An embodiment includes components operating in the digital domain, where a sampled input signal is multiplied by cosine and sine terms to provide est...	03/31/2009
7501904	Low power and duty cycle error free matched current phase locked loop A phase locked loop with a voltage controlled oscillator, where the voltage controlled oscillator includes a feedback loop and delay cells connected in a ring. Each delay cell has a biased pMOSFET to provide pull-up current and a biased nMOSFET to provide pull-down ...	03/10/2009
7501869	Low power, low phase jitter, and duty cycle error insensitive clock receiver architecture and circuits for source synchronous digital data communication A clock receiver architecture for source synchronous digital data communication, the receiver including a forwarded clock amplifier to provide the received forwarded clock signal to a plurality of delay locked loops. Each delay locked loops provides to one or more p...	03/10/2009
7501863	Voltage margining with a low power, high speed, input offset cancelling equalizer A switched-capacitor circuit that may be used for equalization, but configurable for voltage margining. The switched-capacitor circuit cancels the offset voltage inherent in an amplifier and sets the common mode of an input signal at half the rail voltage. Two capac...	03/10/2009
7498892	Split-biased interpolated voltage-controlled oscillator and phase locked loop A voltage-controlled oscillator (VCO) of ring-connected stages, where each stage in the VCO has a first set of differential inverters biased by variable bias voltages, and a second set of differential inverters biased by fixed bias voltages. The differential inverte...	03/03/2009
7402985	Dual path linear voltage regulator A voltage regulator comprising two feedback loops for regulating a load voltage, where the first feedback loop comprises a pass transistor to source current to the load, and the second feedback loop comprises a shunt transistor to shunt current from the pass transis...	07/22/2008
7382197	Adaptive tuning circuit to maximize output signal amplitude for an amplifier An adaptive tuning circuit to maximize the output signal amplitude of a band-pass amplifier, comprising a control circuit to tune the peak frequency of the amplifier by monitoring the change in the output signal amplitude over two successive time sampling intervals....	06/03/2008
7292069	Locally asynchronous, block-level synchronous, configurable logic blocks with sub-threshold analog circuits Embodiments utilize analog sub-threshold circuits to perform Boolean logic and soft-gate logic. These analog circuits may be grouped into configurable logic blocks that are locally asynchronous, but block-level synchronous. The Boolean logic, or function, performed ...	11/06/2007
6856172	Sequential logic circuit for frequency division A circuit to divide down the frequency of a clock signal, where embodiment circuits comprise a set-reset flip-flop feeding its output to a shift register, and combinational logic to provide feedback from the shift register to the set input port, reset input port, or...	02/15/2005
6838957	Differential metal oxide semiconductor capacitor According to an embodiment of the present invention, a capacitor comprising field effect transistors and a bias transistor. ...	01/04/2005
6828857	High gain, high bandwidth CMOS transimpedance amplifier A three-stage transimpedance amplifier, where the first stage is a shunt-shunt feedback amplifier, the second stage is a simple voltage amplifier, and the third stage is a shunt-shunt feedback amplifier. The third stage comprises a pMOSFET serially connected with a ...	12/07/2004
6795881	Physical layer and data link interface with ethernet pre-negotiation A word-based interface between a MAC and a PHY, allowing for variable pin counts, variable PHY and MAC data speeds, and variable numbers of connected PHYs. The word-based interface allows for the PHY to provide PHY-to-MAC words to the MAC, and for the MAC to provide...	09/21/2004
6791399	Discrete-time analog filter A discrete-time analog filter, where a filter tap of the filter comprises a voltage-to-current converter, an active current mirror, and a current multiplier to provide a current signal indicative of a weighted sampled voltage signal. The current signals from the fil...	09/14/2004
6791372	Active cascode differential latch An active cascode differential latch for providing a logic output signal indicative of whether or not a first current is greater than a second current. The first and second currents are fed into two input ports of the active cascode differential latch. The active ca...	09/14/2004
6791364	Conditional burn-in keeper for dynamic circuits A dynamic circuit with a conditional keeper for burn-in. In the described embodiments, a conditional keeper is provided which is active only during the burn-in test, where the conditional keeper is sized larger than the standard keepers so as to compensate for addit...	09/14/2004
6782249	Quadrature signal generation in an integrated direct conversion radio receiver A receiver for direct conversion of RF signals, a particular embodiment comprising a quadrature signal generation circuit having an oscillator with an oscillation frequency of ⅔ times that of the carrier frequency of the RF signal. For the particular embodiment, t...	08/24/2004
6782001	Physical layer and data link interface with reset/sync sharing A word-based interface between a MAC and a PHY, allowing for variable pin counts, variable PHY and MAC data speeds, and variable numbers of connected PHYs. The word-based interface allows for the PHY to provide PHY-to-MAC words to the MAC, and for the MAC to provide...	08/24/2004
6781892	Active leakage control in single-ended full-swing caches A single-ended, full-swing dynamic cache having memory cells grouped into memory groups, where for each memory group one or more foot transistors connect to various memory cells within the memory group. Using a foot transistor reduces sub-threshold leakage current w...	08/24/2004
6777975	Input-output bus interface to bridge different process technologies A bus in which a transmission line is excited by a pMOSFET having a drain connected to the transmission line and having a source at a core voltage VCC, and in which the transmission line is terminated by a device connected to ground. ...	08/17/2004
6771131	CMOS Amplifier for optoelectronic receivers A CMOS amplifier for optoelectronic receivers, the amplifier comprises two transimpedance amplifiers and two differential amplifier latches. One of the two transimpedance amplifiers has an input port to receive a current signal, such as, for example, a current signa...	08/03/2004
6759646	Color interpolation for a four color mosaic pattern An imager with a four color mosaic pattern of red, green, blue, and infrared pass filters, where color component signals for a pixel are interpolated by averaging over nearest neighbor pixels. ...	07/06/2004
6751141	Differential charge transfer sense amplifier A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the...	06/15/2004
6747695	Integrated CMOS imager An integrated CMOS image sensor comprising pixel rows integrated on a substrate, each pixel row having pixel circuits, each pixel circuit providing a voltage signal in response to absorbed photons; and an opaque layer deposited above the pixel rows to define a set o...	06/08/2004
6737924	Differential, double feedback CMOS transimpedance amplifier with noise tolerance A transimpedance amplifier having a first input port to connect to a signal source having an output impedance, and a second input port loaded by an impedance matched to the output impedance of the signal source, the amplifier comprising three stage pairs. The first ...	05/18/2004
6732329	Providing a header checksum for packet data communications A method and apparatus for providing the header checksum of a data packet. ...	05/04/2004
6720756	Modifying acoustic emissions of fans In one embodiment to reduce unwanted acoustic fan noise, the control signal for a computer system cooling fan is modulated so that the acoustic noise power spectral density of the fan has a bandwidth greater than when the control signal is constant. ...	04/13/2004
6718417	Physical layer and data link interface with flexible bus width A word-based interface between a MAC and a PHY, allowing for variable pin counts, variable PHY and MAC data speeds, and variable numbers of connected PHYs. The word-based interface allows for the PHY to provide PHY-to-MAC words to the MAC, and for the MAC to provide...	04/06/2004
6714054	Area efficient waveform evaluation and DC offset cancellation circuits Analog circuits for providing one or more waveform parameters, e.g., the DC offset or average, of an analog input signal. Separate biasing is not necessarily required. Some embodiments comprise field-effect-transistors (FETs) configured in various diode-connected co...	03/30/2004
6707708	Static random access memory with symmetric leakage-compensated bit line An eight-cell for static random access memory, the memory cell comprising cross-coupled inverters to store the information bit, two access nMOSFETs connected to local bit lines to access the stored information bit, and two nMOSFETs each having a gate connected to gr...	03/16/2004
6707318	Low power entry latch to interface static logic with dynamic logic An entry latch to provide a dynamic signal at an output port in response to input static signals at a pulldown network, the pulldown network to conditionally discharge an internal node depending upon the input static signals, the entry latch comprising a pass transi...	03/16/2004
6703882	Dynamic circuits and static latches with low power dissipation A half latch for latching a voltage at a domino gate output with reduced crossbar current duty cycle, comprising a CMOS inverter with input connected to the domino gate output, a first pMOSFET having a gate and drain connected to ground and having a sourc...	03/09/2004
6697980	Die fault testing utilizing an exclusive-or network of gates A method for utilizing an XOR network for testing internal nodes of a die wherein the nodes are connected to the input ports of the XOR network. The nodes are chosen by an iterative algorithm whereby the toggled, but not observed nodes, are partitioned in...	02/24/2004
6693461	Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation An embodiment zipper circuit achieves reduced leakage current by utilizing four voltages so that FETs in the p-logic blocks and n-logic blocks are reversed biased during a pre-charge phase. The FETs in a logic block are also reversed biased during an eval...	02/17/2004

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Attorney: Kalson; Seth Z.